Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
03/2007
03/20/2007US7193823 Magnetoresistive device exhibiting small and stable bias fields independent of device size variation
03/20/2007US7193727 Apparatus and method for mounting or wiring semiconductor chips
03/20/2007US7193726 Optical interferometry
03/20/2007US7193724 Method for measuring thickness of thin film-like material during surface polishing, and surface polishing method and surface polishing apparatus
03/20/2007US7193723 Positioning apparatus and photolithography apparatus including the same
03/20/2007US7193722 Lithographic apparatus with disturbance correction system and device manufacturing method
03/20/2007US7193715 Measurement of overlay using diffraction gratings when overlay exceeds the grating period
03/20/2007US7193713 Method and apparatus for measuring optical characteristic, and projection exposure apparatus using the same
03/20/2007US7193693 Apparatus for manufacturing flat panel display devices
03/20/2007US7193687 Positioning apparatus and method for manufacturing same
03/20/2007US7193686 Lithography apparatus and method for measuring alignment mark
03/20/2007US7193685 Exposure apparatus
03/20/2007US7193684 Pattern mask and exposure for photoresists for patterns and reflection
03/20/2007US7193682 Exposure apparatus and device manufacturing method
03/20/2007US7193681 Lithographic apparatus and device manufacturing method
03/20/2007US7193597 Semiconductor integrated circuit and liquid crystal display device
03/20/2007US7193493 Alignment apparatus, exposure apparatus, and device manufacturing method
03/20/2007US7193369 Method for generating gas plasma
03/20/2007US7193352 Thin film bulk acoustic wave sensor suite
03/20/2007US7193339 Positioning apparatus and charged-particle-beam exposure apparatus
03/20/2007US7193330 Semiconductor device with improved design freedom of external terminal
03/20/2007US7193328 Semiconductor device
03/20/2007US7193325 Reliability improvement of SiOC etch with trimethylsilane gas passivation in Cu damascene interconnects
03/20/2007US7193323 Copper tungsten phosphide formed by electrodeposition of layers
03/20/2007US7193322 Sacrificial shallow trench isolation oxide liner for strained-silicon channel CMOS devices
03/20/2007US7193321 IC package, inspection method of IC package mounting body, repairing method of IC package mounting body, and inspection pin for IC package mounting body
03/20/2007US7193315 Test vehicle grid array package
03/20/2007US7193312 Castellation wafer level packaging of integrated circuit chips
03/20/2007US7193311 Multi-chip circuit module and method for producing the same
03/20/2007US7193308 Intermediate chip module, semiconductor device, circuit board, and electronic device
03/20/2007US7193307 Multi-layer FET array and method of fabricating
03/20/2007US7193306 Semiconductor structure having stacked semiconductor devices
03/20/2007US7193304 Memory card structure
03/20/2007US7193301 Semiconductor device and manufacturing method thereof
03/20/2007US7193297 Semiconductor device, method for manufacturing the same, circuit substrate and electronic device
03/20/2007US7193296 Semiconductor substrate
03/20/2007US7193293 Semiconductor component with a compensation layer, a depletion zone, and a complementary depletion zone, circuit configuration with the semiconductor component, and method of doping the compensation layer of the semiconductor component
03/20/2007US7193287 Magnetic memory device, a method for manufacturing a magnetic memory device, and an integrated circuit device including such magnetic memory device
03/20/2007US7193285 Tilted array geometry for improved MRAM switching
03/20/2007US7193284 Magnetoresistance effect element, method of manufacture thereof, magnetic storage and method of manufacture thereof
03/20/2007US7193281 Semiconductor device and process for producing the same
03/20/2007US7193280 Indium oxide conductive film structures
03/20/2007US7193278 Static random access memories (SRAMS) having vertical transistors
03/20/2007US7193277 Application of different isolation schemes for logic and embedded memory
03/20/2007US7193276 Semiconductor devices with a source/drain regions formed on a recessed portion of an isolation layer
03/20/2007US7193275 Semiconductor device allowing modulation of a gain coefficient and a logic circuit provided with the same
03/20/2007US7193273 Method for enhancing vertical growth during the selective formation of silicon, and structures formed using same
03/20/2007US7193272 Semiconductor device and method of manufacturing the same
03/20/2007US7193271 Transistor having a protruded drain
03/20/2007US7193270 Semiconductor device with a vertical transistor
03/20/2007US7193269 MOS semiconductor device
03/20/2007US7193264 Floating gate transistors
03/20/2007US7193260 Ferroelectric memory device
03/20/2007US7193257 Solid state image sensing device and manufacturing and driving methods thereof
03/20/2007US7193256 Manufacturing method for a semiconductor substrate comprising at least a buried cavity and devices formed with this method
03/20/2007US7193255 Semiconductor device with floating conducting region placed between device elements
03/20/2007US7193253 Transition metal alloys for use as a gate electrode and devices incorporating these alloys
03/20/2007US7193252 Solid-state imaging device and solid-state imaging device array
03/20/2007US7193249 Nitride-based light emitting device and method of manufacturing the same
03/20/2007US7193247 Gallium nitride compound semiconductor device
03/20/2007US7193240 Sequential lateral solidification mask with stripe-shaped portions for transmitting laser light
03/20/2007US7193239 Three dimensional structure integrated circuit
03/20/2007US7193238 Display device and a method for manufacturing the same
03/20/2007US7193232 Lithographic apparatus and device manufacturing method with substrate measurement not through liquid
03/20/2007US7193231 Alignment tool, a lithographic apparatus, an alignment method, a device manufacturing method and device manufactured thereby
03/20/2007US7193210 Composite structure providing steady-state non-equilibrium distribution of free carriers and IR system using same for photon energy up-conversion
03/20/2007US7193193 Magnetic annealing of ferromagnetic thin films using induction heating
03/20/2007US7193157 Flexible circuit board mounted with semiconductor chip and method for mounting semiconductor chip
03/20/2007US7193009 Electronic device using low dielectric loss tangent insulators for high frequency signals
03/20/2007US7192997 Encapsulant composition and electronic package utilizing same
03/20/2007US7192910 Cleaning solutions and etchants and methods for using same
03/20/2007US7192894 High performance CMOS transistors using PMD liner stress
03/20/2007US7192893 Use of linear injectors to deposit uniform selective ozone TEOS oxide film by pulsing reactants on and off
03/20/2007US7192892 Atomic layer deposited dielectric layers
03/20/2007US7192891 Method for forming a silicon oxide layer using spin-on glass
03/20/2007US7192890 Depositing an oxide
03/20/2007US7192889 Methods for forming a high dielectric film
03/20/2007US7192888 Low selectivity deposition methods
03/20/2007US7192887 Semiconductor device with nitrogen in oxide film on semiconductor substrate and method of manufacturing the same
03/20/2007US7192886 Method for using additives in the caustic etching of silicon for obtaining improved surface characteristics
03/20/2007US7192885 Etching with a solution consisting of water, concentrated hydrofluoric acid and concentrated nitric acid at a temperature between 0 and 15 degrees Celsius
03/20/2007US7192884 Method for manufacturing semiconductor laser device
03/20/2007US7192883 Method of manufacturing semiconductor device
03/20/2007US7192882 Component for electromagnetic waves and a method for manufacturing the same
03/20/2007US7192881 Method of forming sidewall spacer elements for a circuit element by increasing an etch selectivity
03/20/2007US7192880 Method for line etch roughness (LER) reduction for low-k interconnect damascene trench etching
03/20/2007US7192879 Method for manufacturing micro-structural unit
03/20/2007US7192878 Method for removing post-etch residue from wafer surface
03/20/2007US7192877 Low-K dielectric etch process for dual-damascene structures
03/20/2007US7192876 Transistor with independent gate structures
03/20/2007US7192875 Etching with the gas composition selecting from CIF3, BrF3, BrF5 and IF5; restore the surfaces; semiconductors
03/20/2007US7192874 Method for reducing foreign material concentrations in etch chambers
03/20/2007US7192873 Doping the substrate through spaces formed by selectively removing the nano particles, without using a mask or a fine pattern; atomic layer deposition for depositing a dielectric layer and a metal layer
03/20/2007US7192872 Method of manufacturing semiconductor device having composite buffer layer
03/20/2007US7192871 Semiconductor device with a line and method of fabrication thereof
03/20/2007US7192870 Semiconductor device and fabrication process therefor
03/20/2007US7192869 Methods for planarizing a metal layer
03/20/2007US7192868 Method of obtaining release-standing micro structures and devices by selective etch removal of protective and sacrificial layer using the same
03/20/2007US7192867 Protection of low-k dielectric in a passivation level
03/20/2007US7192866 Source alternating MOCVD processes to deposit tungsten nitride thin films as barrier layers for MOCVD copper interconnects