Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
07/2005
07/21/2005US20050157552 Programming non-volatile memory
07/21/2005US20050157551 Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
07/21/2005US20050157550 Nonvolatile memory system, semiconductor memory and writing method
07/21/2005US20050157548 Nonvolatile semiconductor storage device
07/21/2005US20050157546 Precharging the write path of an MRAM device for fast write operation
07/21/2005US20050157545 Magnetoresistive element and magnetic memory unit
07/21/2005US20050157544 Magnetic tunneling junction film structure with process determined in-plane magnetic anisotropy
07/21/2005US20050157542 Magnetoresistive element and magnetic memory unit
07/21/2005US20050157541 Magnetic random access memory
07/21/2005US20050157540 Soft-reference four conductor magnetic memory storage device
07/21/2005US20050157539 Memories and memory circuits
07/21/2005US20050157538 Magnetic storage device using ferromagnetic tunnel function element
07/21/2005US20050157537 Static random access memory
07/21/2005US20050157536 Semiconductor device including nonvolatile memory and method of fabricating the same
07/21/2005US20050157535 Organic-polymer memory element
07/21/2005US20050157534 DRAM refreshment
07/21/2005US20050157533 Memory array having 2t memory cells
07/21/2005US20050157532 Ferroelectric memory device, electronic apparatus and driving method
07/21/2005US20050157531 Memory device of ferro-electric
07/21/2005US20050157530 Ferroelectric memory
07/21/2005US20050157527 Semiconductor memory device
07/21/2005US20050157526 Semiconductor device
07/21/2005US20050157144 Print media transport assembly
07/21/2005US20050157108 Printhead assembly
07/21/2005US20050157084 Printhead nozzle arrangement with a micro-electromechanical shape memory alloy based actuator
07/21/2005US20050157080 Printing mechanism having wide format printing zone
07/21/2005US20050157066 Inkjet print assembly for high volume pagewidth printing
07/21/2005US20050156652 Level converter
07/21/2005US20050156647 Delay signal generator circuit and memory system including the same
07/21/2005US20050156646 Method and system of calibrating the control delay time
07/21/2005US20050156627 Programmable array logic circuit employing non-volatile ferromagnetic memory cells
07/21/2005US20050156271 Data storage device
07/21/2005US20050156217 Semiconductor memory device and method for fabricating the same
07/21/2005US20050156216 Ferroelectric capacitor and method of manufacturing the same
07/21/2005DE4336720B4 Eingabepuffer Input buffer
07/21/2005DE10360030A1 Semiconductor memory with numerous memory cells addressable by word and bit lines, with at least two current generators, first generating preset current ono selected bit lines and/or preset word line with memory in active working mode
07/21/2005DE10358038A1 Integrierte Schaltung zur Speicherung von Betriebsparametern An integrated circuit for storage of operating parameters
07/21/2005DE102004060644A1 Direktzugriffsspeicher unter Verwendung von Vorladezeitgebern in einem Testmodus Random access memory using Vorladezeitgebern in a test mode
07/21/2005DE102004060579A1 Verfahren und Vorrichtung zum Steuern von Auffrischzyklen eines Mehrzyklusauffrischschemas bei einem dynamischen Speicher Method and apparatus for controlling a refresh of a dynamic memory in Mehrzyklusauffrischschemas
07/21/2005DE102004060571A1 Slew rate adjusting apparatus for e.g. synchronous dynamic RAM, has slew rate control signal generation block to output slew rate control signals, and data output buffer adjusting slew rate of data signal input by control signals
07/21/2005DE102004040506A1 Adressierschaltung für ein Kreuzungspunkt-Speicherarray, das Kreuzungspunkt-Widerstandselemente umfasst Addressing circuitry comprises a cross-point memory array, the cross point resistor elements
07/20/2005EP1555755A2 Digitally Controlled Delay Circuit
07/20/2005EP1555694A1 Spin transistor using spin filter effect and nonvolatile memory using spin transistor
07/20/2005EP1554731A2 Cascode sense amp and column select circuit and method of operation
07/20/2005EP1481398B1 A memory cell
07/20/2005EP1338012B1 Circuit for non-destructive, self-normalizing reading-out of mram memory cells
07/20/2005EP1116043B1 Method of manufacturing a magnetic tunnel junction device
07/20/2005CN1643615A Method for producing a reference layer and an MRAM memory cell provided with said type of reference layer
07/20/2005CN1643614A Composite storage circuit and semiconductor device having the same
07/20/2005CN1643613A Data storage circuit, data write method in the data storage circuit, and data storage device
07/20/2005CN1643612A Magnetoresistive memory devices and assemblies; and methods of storing and retrieving information
07/20/2005CN1643611A Increasing the read signal in ferroelectric memories
07/20/2005CN1643610A Asynchronous interface circuit and method for a pseudo-static memory device
07/20/2005CN1641984A Precision margining circuitry
07/20/2005CN1641874A 多芯片封装 Multi-chip package
07/20/2005CN1641792A Power supply start reset release device and method
07/20/2005CN1641791A Concurrent refresh mode with distributed row address counters in an embedded DRAM
07/20/2005CN1211873C Magnetic resistance element and magnetic device using same
07/20/2005CN1211872C Magnetoresistive memory having improved interference immunity
07/20/2005CN1211852C Nonvolatile memory and method of driving nonvolatile memory
07/19/2005US6920540 Timing calibration apparatus and method for a memory device signaling system
07/19/2005US6920536 Method of accessing matrix data with address translation circuit that enables quick serial access in row or column directions
07/19/2005US6920524 Detection circuit for mixed asynchronous and synchronous memory operation
07/19/2005US6920523 Bank address mapping according to bank retention time in dynamic random access memories
07/19/2005US6920522 Synchronous flash memory with accessible page during write
07/19/2005US6920081 Apparatus for latency specific duty cycle correction
07/19/2005US6920080 Methods for generating output control signals in synchronous semiconductor memory devices and related semiconductor memory devices
07/19/2005US6920079 Semiconductor device and semiconductor memory device
07/19/2005US6920078 CMOS image sensor having row decoder capable of shutter timing control
07/19/2005US6920077 Graphics controller integrated circuit without memory interface
07/19/2005US6920075 Amplifier for reading storage cells with exclusive-OR type function
07/19/2005US6920074 Method for reading a memory cell in a semiconductor memory, and semiconductor memory
07/19/2005US6920071 Semiconductor integrated circuit device
07/19/2005US6920068 Semiconductor memory device with modified global input/output scheme
07/19/2005US6920066 Programming method of the memory cells in a multilevel non-volatile memory device
07/19/2005US6920065 Magnetic storage element, recording method using the same, and magnetic storage device
07/19/2005US6920064 Magneto-resistive memory cell structures with improved selectivity
07/19/2005US6920063 Magnetic element utilizing spin transfer and an MRAM device using the magnetic element
07/19/2005US6920062 System and method for reading data stored on a magnetic shift register
07/19/2005US6920061 Loadless NMOS four transistor dynamic dual Vt SRAM cell
07/19/2005US6920060 Memory device, circuits and methods for operating a memory device
07/19/2005US6920059 Reducing effects of noise coupling in integrated circuits with memory arrays
07/19/2005US6920058 Semiconductor memory device
07/19/2005US6919871 Light emitting display, display panel, and driving method thereof
07/19/2005US6919756 Method and circuit for adjusting a voltage upon detection of a command applied to an integrated circuit
07/19/2005US6919745 Ring-resister controlled DLL with fine delay line and direct skew sensing detector
07/19/2005US6919738 Output buffer circuit, memory chip, and semiconductor device having a circuit for controlling buffer size
07/19/2005US6919613 Magnetic tunneling junction antifuse device
07/19/2005US6919595 Semiconductor memory device
07/19/2005US6919594 Magneto resistive storage device having a magnetic field sink layer
07/19/2005US6919591 Thin film transistor array panel for a liquid crystal display
07/19/2005US6919254 Computer systems, processes for forming a SRAM cell, processes for turning a SRAM cell off, processes for writing a SRAM cell and processes for reading data from a SRAM cell
07/19/2005US6919213 Methods for operating a unipolar spin transistor and applications of same
07/19/2005US6918707 Keyboard printer print media transport assembly
07/19/2005US6918654 Ink distribution assembly for an ink jet printhead
07/19/2005US6918542 Data distribution mechanism in the form of ink dots on cards
07/14/2005WO2005064783A2 Tuneable spin torque device for generating an oscillating signal and method for tuning
07/14/2005WO2005064616A1 Synchronization devices having input/output delay model tuning elements
07/14/2005WO2005064615A2 Memory gain cell
07/14/2005WO2005064614A1 Non-volatile ferroelectric thin film device using an organic ambipolar semiconductor and method for processing such a device
1 ... 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 ... 761