Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
06/2005
06/21/2005US6909638 Non-volatile memory having a bias on the source electrode for HCI programming
06/21/2005US6909637 Full rail drive enhancement to differential SEU hardening circuit while loading data
06/21/2005US6909635 Programmable memory cell using charge trapping in a gate oxide
06/21/2005US6909633 MRAM architecture with a flux closed data storage layer
06/21/2005US6909632 Multiple modes of operation in a cross point array
06/21/2005US6909631 MRAM and methods for reading the MRAM
06/21/2005US6909630 MRAM memories utilizing magnetic write lines
06/21/2005US6909629 MRAM signal size increasing apparatus and methods
06/21/2005US6909628 High density magnetic RAM and array architecture using a one transistor, one diode, and one MTJ cell
06/21/2005US6909627 Apparatus turning on word line decoder by reference bit line equalization
06/21/2005US6909626 Method and related circuit for accessing locations of a ferroelectric memory
06/21/2005US6909625 Method to produce data cell region and system region for semiconductor memory
06/21/2005US6909315 Data strobe signals (DQS) for high speed dynamic random access memories (DRAMs)
06/21/2005US6909312 Synchronization circuit and synchronization method
06/21/2005US6909159 Method and apparatus to make a semiconductor chip susceptible to radiation failure
06/21/2005US6909130 Magnetic random access memory device having high-heat disturbance resistance and high write efficiency
06/21/2005US6909129 Magnetic random access memory
06/21/2005US6908808 Method of forming and storing data in a multiple state memory cell
06/21/2005US6908772 Single transistor ferroelectric memory cell, device and method for the formation of the same incorporating a high temperature ferroelectric gate dielectric
06/16/2005WO2005055425A1 Nonvolatile flip-flop circuit, and method for driving the same
06/16/2005WO2005055242A1 Method and apparatus to improve memory performance
06/16/2005WO2004032145A3 Programmable magnetic memory device
06/16/2005US20050132158 Memory device signaling system and method with independent timing calibration for parallel signal paths
06/16/2005US20050132131 Partial bank DRAM precharge
06/16/2005US20050130374 Methods for contacting conducting layers overlying magnetoelectronic elements of MRAM devices
06/16/2005US20050129025 Random access memory initialization
06/16/2005US20050128860 Thin film magnetic memory device including memory cells having a magnetic tunnel junction
06/16/2005US20050128859 Delay circuit, ferroelectric memory device and electronic equipment
06/16/2005US20050128857 X address extractor and memory for high speed operation
06/16/2005US20050128856 X address extractor and method for extracting X-address in memory device
06/16/2005US20050128855 Self timed bit and read/write pulse stretchers
06/16/2005US20050128854 Synchronous controlled, self-timed local SRAM block
06/16/2005US20050128853 Semiconductor device including multi-chip
06/16/2005US20050128852 High performance sram device and method of powering-down the same
06/16/2005US20050128851 Data storage device and refreshing method for use with such device
06/16/2005US20050128849 Semiconductor memory device and method of reading data
06/16/2005US20050128848 Method to reduce switch threshold of soft magnetic films
06/16/2005US20050128847 Refresh controller with low peak current
06/16/2005US20050128844 Semiconductor integrated circuit
06/16/2005US20050128840 Cross point memory array exhibiting a characteristic hysteresis
06/16/2005US20050128839 Semiconductor memory device
06/16/2005US20050128837 Random access memory using precharge timers in test mode
06/16/2005US20050128835 Semiconductor device which is low in power and high in speed and is highly integrated
06/16/2005US20050128833 Semiconductor memory device having access time control circuit
06/16/2005US20050128828 Methods and circuits for latency control in accessing memory devices
06/16/2005US20050128825 Circuit for generating data strobe signal in semiconductor device and method thereof
06/16/2005US20050128821 High-voltage generator circuit and semiconductor memory device including the same
06/16/2005US20050128819 Electrically alterable non-volatile multi-level memory device and method of operating such a device
06/16/2005US20050128818 Memory circuit and method of generating the same
06/16/2005US20050128816 Floating trap non-volatile semiconductor memory devices including high dielectric constant blocking insulating layers
06/16/2005US20050128814 Method of programming a flash memory through boosting a voltage level of a source line
06/16/2005US20050128811 Nonvolatile semiconductor memory device capable of uniformly inputting/outputting data
06/16/2005US20050128810 Self-boosting technique
06/16/2005US20050128808 Semiconductor memory device and memory system
06/16/2005US20050128805 Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
06/16/2005US20050128804 Multi-state NROM device
06/16/2005US20050128803 Gated diode memory cells
06/16/2005US20050128802 Magnetic memory device and method for production thereof
06/16/2005US20050128801 Magnetic random access memory device and a method of switching a magnetic orientation of memory elements therein
06/16/2005US20050128800 Thin film magnetic memory device conducting read operation by a self-reference method
06/16/2005US20050128799 Semiconductor integrated circuit device
06/16/2005US20050128798 Phase change resistor cell and nonvolatile memory device using the same
06/16/2005US20050128797 Enhanced read and write methods for negative differential resistance (NDR) based memory device
06/16/2005US20050128796 Method for improving the read signal in a memory having passive memory elements
06/16/2005US20050128795 Reducing power consumption during MRAM writes using multiple current levels
06/16/2005US20050128794 Method and apparatus for a high density magnetic random access memory (mram) with stackable architecture
06/16/2005US20050128793 Method and apparatus for a low write current MRAM having a write magnet
06/16/2005US20050128792 Memory system and semiconductor integrated circuit
06/16/2005US20050128790 Static random access memory device having reduced leakage current during active mode and a method of operating thereof
06/16/2005US20050128789 SRAM device and a method of operating the same to reduce leakage current during a sleep mode
06/16/2005US20050128788 Patterned nanoscopic articles and methods of making the same
06/16/2005US20050128787 Method of forming a memory device having a storage transistor
06/16/2005US20050128786 Semiconductor memory device
06/16/2005US20050128785 Phase change resistor cell, nonvolatile memory device and control method using the same
06/16/2005US20050128784 Ferroelectric memory and data reading method for same
06/16/2005US20050128783 Ferroelectric memory cell array and device for operating the same
06/16/2005US20050128782 Ferroelectric memory device having a reference voltage generating circuit
06/16/2005US20050128781 Hybrid switch cell and memory device using the same
06/16/2005US20050128780 Semiconductor integrated circuit device
06/16/2005US20050128779 Imprint suppression circuit scheme
06/16/2005US20050128303 Method for manipulating and printing captured images
06/16/2005US20050128252 Motion transmitting structure
06/16/2005US20050128019 Refresh oscillator
06/16/2005US20050128009 Low power self refresh timer oscillator
06/16/2005US20050127985 Semiconductor device having logic circuit and macro circuit
06/16/2005US20050127971 Redundant single event upset supression system
06/16/2005US20050127940 Signal transmitting device suited to fast signal transmission
06/16/2005US20050127429 Semiconductor nonvolatile memory device
06/16/2005US20050127419 Semiconductor integrated circuit device
06/16/2005US20050127418 Low magnetization materials for high performance magnetic memory devices
06/16/2005US20050127416 MRAM cell with flat topography and controlled bit line to free layer distance and method of manufacture
06/16/2005US20050127403 RRAM circuit with temperature compensation
06/16/2005US20050127380 Transistor and semiconductor device
06/16/2005US20050127350 Field emission phase change diode memory
06/16/2005US20050127349 Phase change tip storage cell
06/16/2005US20050127191 Data storage device incorporating a two-dimensional code
06/16/2005US20050127181 Printing cartridge with two dimensional code indentification
06/16/2005DE10350168A1 Speicheranordnung und Verfahren zum Betreiben einer solchen Memory device and method of operating such a
06/16/2005DE10345976A1 Test device for testing a circuit unit applies a test system, a register device for storing initializing data, a control unit and a switch-on unit
06/16/2005DE10326925A1 Speichersystem und Steuerungsverfahren dafür Storage system and control method thereof
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