Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
05/2005
05/31/2005US6901025 Nonvolatile semiconductor memory device which can be programmed at high transfer speed
05/31/2005US6901024 Multi-port semiconductor memory device having reduced bitline voltage offset and method for arranging memory cells thereof
05/31/2005US6901022 Proportional to temperature voltage generator
05/31/2005US6901020 Integrated charge sensing scheme for resistive memories
05/31/2005US6901018 Method of generating initializing signal in semiconductor memory device
05/31/2005US6901017 Semiconductor memory having hierarchical bit line structure
05/31/2005US6901016 Semiconductor memory device and electronic instrument using the same
05/31/2005US6901014 Circuits and methods for screening for defective memory cells in semiconductor memory devices
05/31/2005US6901007 Memory device with multi-level storage cells and apparatuses, systems and methods including same
05/31/2005US6901006 Semiconductor integrated circuit device including first, second and third gates
05/31/2005US6901005 Method and system reading magnetic memory
05/31/2005US6901003 Lower power and reduced device split local and continuous bitline for domino read SRAMs
05/31/2005US6901002 Ferroelectric memory
05/31/2005US6901001 Ferroelectric memory input/output apparatus
05/31/2005US6900664 Method and system for intelligent bi-direction signal net with dynamically configurable input/output cell
05/31/2005US6900517 Non-volatile memory with phase-change recording layer
05/31/2005US6900503 SRAM formed on SOI substrate
05/31/2005US6900491 Magnetic memory
05/31/2005US6900490 Magnetic random access memory
05/31/2005US6900478 Multi-threshold MIS integrated circuit device and circuit design method thereof
05/31/2005US6900468 Indium chalcogenide, gallium chalcogenide, and indium-gallium chalcogenide phase-change media for ultra-high-density data-storage devices
05/31/2005US6900064 Method for manufacturing NAND type nonvolatile ferroelectric memory cell
05/26/2005WO2005048296A2 Nanotube-based switching elements with multiple controls and circuits made from same
05/26/2005WO2005048268A2 Nrom flash memory with self-aligned structural charge separation
05/26/2005WO2005048266A1 Nonvolatile semiconductor memory device
05/26/2005WO2005048265A1 Method and system for performing readout utilizing a self reference scheme
05/26/2005WO2005048262A2 Mram architecture with a flux closed data storage layer
05/26/2005WO2005048244A1 Bias-adjusted giant magnetoresistive (gmr) devices for magnetic random access memory (mram) applications
05/26/2005WO2004093086A3 Magnetically lined conductors
05/26/2005WO2004053880A3 Mram memories utilizing magnetic write lines
05/26/2005US20050114622 Memory module and memory-assist module
05/26/2005US20050114613 Multi-chip package type memory system
05/26/2005US20050114588 Method and apparatus to improve memory performance
05/26/2005US20050112896 Multi-bit phase change memory cell and multi-bit phase change memory including the same, method of forming a multi-bit phase change memory, and method of programming a multi-bit phase change memory
05/26/2005US20050111583 Delay device, power supply device, and program product for delaying signal
05/26/2005US20050111341 Molecular optoelectronic memory device
05/26/2005US20050111293 Synchronous semiconductor device, and inspection system and method for the same
05/26/2005US20050111291 Clock signal synchronizing device, and clock signal synchronizing method
05/26/2005US20050111288 Semiconductor memory device and storage method thereof
05/26/2005US20050111287 Imprint-free coding for ferroelectric nonvolatile counters
05/26/2005US20050111284 Semiconductor device with multi-bank DRAM and cache memory
05/26/2005US20050111282 Semiconductor memory device with refreshment control
05/26/2005US20050111279 Process for making and programming and operating a dual-bit multi-level ballistic MONOS memory
05/26/2005US20050111275 Cost efficient row cache for DRAMs
05/26/2005US20050111274 Dual power sensing scheme for a memory device
05/26/2005US20050111271 Molecular memory cell
05/26/2005US20050111268 Semiconductor memory device to supply stable high voltage during auto-refresh operation and method therefor
05/26/2005US20050111267 Semiconductor integrated circuit device
05/26/2005US20050111265 Semiconductor device using SCL circuit
05/26/2005US20050111263 Cross point array using distinct voltages
05/26/2005US20050111260 Boosted substrate/tub programming for flash memories
05/26/2005US20050111257 Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
05/26/2005US20050111256 Device with switchable capacitance
05/26/2005US20050111255 Floating-body dynamic random access memory with purge line
05/26/2005US20050111254 Magnetic memory device and methods for making same
05/26/2005US20050111253 Apparatus and method of analyzing a magnetic random access memory
05/26/2005US20050111252 Field effect device with a channel with a switchable conductivity
05/26/2005US20050111251 Memory cell structure
05/26/2005US20050111249 Disk array optimizing the drive operation time
05/26/2005US20050111137 Ultrafast pulse field source utilizing optically induced magnetic transformation
05/26/2005US20050110983 Phase change memory devices with contact surface area to a phase changeable material defined by a sidewall of an electrode hole and methods of forming the same
05/26/2005US20050110899 Digital camera with printing assembly
05/26/2005US20050110847 Printhead chip incorporating laterally displaceable ink flow control mechanisms
05/26/2005US20050110842 Printhead chip that incorporates micro-mechanical translating mechanisms
05/26/2005US20050110841 Printhead chip incorporating double action shutter mechanisms
05/26/2005US20050110840 Printhead chip incorporating a double action ink ejection mechanism
05/26/2005US20050110839 Printhead chip incorporating electro-magnetically operable ink ejection mechanisms
05/26/2005US20050110838 Printhead chip that incorporates pivotal micro-mechanical ink ejecting mechanisms
05/26/2005US20050110837 Micro-electromechanical device for dispensing fluid
05/26/2005US20050110826 Printhead chip that incorporates micro-mechanical lever mechanisms
05/26/2005US20050110592 Self refresh oscillator
05/26/2005US20050110561 Precision margining circuitry
05/26/2005US20050110560 Apparatus and method for stabilizing a boosted voltage, apparatus and method for generating a boosted voltage having the same
05/26/2005US20050110542 Delay locked loop capable of performing reliable locking operation
05/26/2005US20050110540 Delay locked loop and its control method
05/26/2005US20050110516 Semiconductor device
05/26/2005US20050110117 3d rram
05/26/2005US20050110004 Magnetic tunnel junction with improved tunneling magneto-resistance
05/26/2005CA2535634A1 Nanotube-based switching elements with multiple controls and circuits made from same
05/25/2005EP1533905A2 Imprint-free coding for ferroelectric nonvolatile counters
05/25/2005EP1533901A2 CMOS circuits with protection for a single event upset
05/25/2005EP1533846A1 Large-capacity magnetic memory using carbon nano-tube
05/25/2005EP1533815A2 3d rram
05/25/2005EP1533703A2 Method for controlling non-volatile semiconductor memory system
05/25/2005EP1532684A1 Ferroelectric device and method of manufacturing such a device
05/25/2005EP1532635A1 Method of programming a multi-level memory device
05/25/2005EP1344223A4 Organic bistable device and organic memory cells
05/25/2005EP0675502B1 Multiple sector erase flash EEPROM system
05/25/2005DE102004024377A1 Wärmeunterstützte Schaltarraykonfiguration für MRAM Heat-assisted switching array configuration for MRAM
05/25/2005CN1620716A A method of improving surface planarity prior to MRAM bit material deposition
05/25/2005CN1620703A Novel method and structure for efficient data verification operation for non-volatile memories
05/25/2005CN1620702A Method and system for programming and inhibiting multi-level, non-volatile memory cells
05/25/2005CN1620700A 混合密度存储卡 Mixed Density Memory Card
05/25/2005CN1620699A A programmable conductor random access memory and a method for writing thereto
05/25/2005CN1620698A System and method for inhibiting imprinting of capacitor structures of a memory
05/25/2005CN1620697A MRAM without isolation devices
05/25/2005CN1620696A Multi-mode synchronous memory device and methods of operating and testing same
05/25/2005CN1619966A Delay locked loop and its control method
05/25/2005CN1619706A Memory cell signal window testing apparatus
05/25/2005CN1619700A MRAM cell, array, and MRAM cell formularizing method
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