| Patents for G06F 5 - Methods or arrangements for data conversion without changing the order or content of the data handled (8,116) |
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| 05/04/2004 | US6732131 Discrete cosine transformation apparatus, inverse discrete cosine transformation apparatus, and orthogonal transformation apparatus |
| 04/29/2004 | WO2003007517A8 Automatic adjustment of buffer depth |
| 04/29/2004 | US20040083250 Data processing device having a central processing unit and digital signal processing unit-- |
| 04/29/2004 | US20040081317 Encryption circuit achieving higher operation speed |
| 04/29/2004 | US20040080274 Intelligent electrical switching device |
| 04/28/2004 | EP1413076A1 Automatic adjustment of buffer depth |
| 04/28/2004 | EP1412859A1 Data formatter employing data shifter based on the destination address |
| 04/28/2004 | EP0960504B1 Multicopy queue structure with searchable cache area |
| 04/27/2004 | US6728722 General data structure for describing logical data spaces |
| 04/27/2004 | US6728654 Random number indexing method and apparatus that eliminates software call sequence dependency |
| 04/22/2004 | US20040076191 Method and a communiction apparatus in a communication system |
| 04/22/2004 | DE10391056T5 Zusatzgerät-Steuerschnittstelle Accessory control interface |
| 04/21/2004 | EP1410509A2 Non-power-of-two gray-code counter system having binary incrementer with counts distributed with bilateral symmetry |
| 04/21/2004 | EP1410158A2 Power controlled electronic circuit |
| 04/21/2004 | EP0960511B1 Method and apparatus for reclaiming buffers |
| 04/21/2004 | CN1491381A Method and system for buffering streamed data |
| 04/20/2004 | US6725388 Method and system for performing link synchronization between two clock domains by inserting command signals into a data stream transmitted between the two clock domains |
| 04/20/2004 | US6725299 FIFO overflow management |
| 04/20/2004 | US6725298 Method and system for filter-processing by ensuring a memory space for a ring-buffer in digital signal processor |
| 04/20/2004 | US6725292 Direct memory access controller for circular buffers |
| 04/20/2004 | US6724846 Simple, high performance, bit-sliced mesochronous synchronizer for a source synchronous link |
| 04/20/2004 | US6724683 Transferring data between different clock domains |
| 04/15/2004 | WO2003023600A3 An apparatus and method for extracting and loading data to/from a buffer |
| 04/15/2004 | US20040071151 Asynchronous control circuit with symmetric forward and reverse latencies |
| 04/15/2004 | US20040070793 Information processing methodology |
| 04/14/2004 | CN1145877C Multibit shifting appartus, data processor using same, and method therefor |
| 04/13/2004 | US6721897 Bus control circuit effecting timing control using cycle registers for respective cycles holding signal levels corresponding to bus control signals that are output by arrangement of signal level |
| 04/13/2004 | US6721895 Data communications system and data communications method |
| 04/13/2004 | US6721827 Data processing apparatus and data processing method |
| 04/13/2004 | US6721826 Buffer partitioning for managing multiple data streams |
| 04/13/2004 | US6721825 Method to control data reception buffers for packetized voice channels |
| 04/08/2004 | WO2004029793A1 Computationally efficient mathematical engine |
| 04/08/2004 | WO2004021113A3 Method and apparatus for downloading executable code in a non-disruptive manner |
| 04/08/2004 | US20040066697 Multiport memory circuit composed of 1Tr-1C memory cells |
| 04/08/2004 | CA2499929A1 Computationally efficient mathematical engine |
| 04/07/2004 | CA2439737A1 Extented time-code for multimedia presentations |
| 04/07/2004 | CA2439733A1 Time references for multimedia objects |
| 04/06/2004 | US6718456 Parallel pack instruction method and apparatus |
| 04/06/2004 | US6718401 System and method for device support |
| 04/06/2004 | US6717624 Line memory in which reading of a preceding line from a first memory and writing of a current line to a second memory are performed in the same time period |
| 04/01/2004 | WO2004027596A1 Apparatus and method for dynamic program decompression |
| 04/01/2004 | US20040064640 Queuing architecture including a plurality of queues and associated method for controlling admission for disk access requests for video content |
| 04/01/2004 | CA2498036A1 Apparatus and method for dynamic program decompression |
| 03/31/2004 | EP1402340A2 First-in, first-out memory system and method thereof |
| 03/31/2004 | EP1402339A1 Fifo buffer that can read and/or write a selectable number of data words per bus cycle |
| 03/31/2004 | CN1144371C Length changeable code and device for dividing the length changeable code word |
| 03/31/2004 | CN1144213C Method and apparatus for decoding |
| 03/30/2004 | US6715010 Bus emulation apparatus |
| 03/30/2004 | US6715002 Watermark for additional data burst into buffer memory |
| 03/30/2004 | US6714957 System and method for efficient processing of denormal results as hardware exceptions |
| 03/30/2004 | US6714146 Code converter and method of code conversion |
| 03/25/2004 | WO2003046757A3 System and method for processing extensible markup language (xml) documents |
| 03/25/2004 | US20040059892 Apparatus and method for dynamic program decompression |
| 03/25/2004 | US20040059840 Method and apparatus for the dynamic scheduling of device commands |
| 03/23/2004 | US6711696 Method for transfering data between two different clock domains by calculating which pulses of the faster clock domain should be skipped substantially simultaneously with the transfer |
| 03/23/2004 | US6711494 Data formatter for shifting data to correct data lanes |
| 03/23/2004 | US6711227 Synchronizing method and apparatus |
| 03/18/2004 | US20040054692 Method for compressing/decompressing a structured document |
| 03/18/2004 | US20040051652 Data receiving device for receiving serial data according to over-sampling |
| 03/17/2004 | EP0976226B1 Integrated multiport switch having shared media access control circuitry |
| 03/17/2004 | CN1483161A Modulo addressing |
| 03/16/2004 | US6707411 Analog-to-digital converter with on-chip memory |
| 03/11/2004 | WO2004021113A2 Method and apparatus for downloading executable code in a non-disruptive manner |
| 03/11/2004 | US20040049485 Method for storing data, method for reading data, apparatus for storing data and apparatus for reading data |
| 03/11/2004 | CA2496946A1 Method and apparatus for downloading executable code in a non-disruptive manner |
| 03/10/2004 | EP1396786A1 Bridge circuit for use in retiming in a semiconductor integrated circuit |
| 03/09/2004 | US6704882 Data bit-to-clock alignment circuit with first bit capture capability |
| 03/04/2004 | WO2004019202A2 Fifo clock domain change |
| 03/04/2004 | US20040044997 Method and apparatus for downloading executable code in a non-disruptive manner |
| 03/04/2004 | US20040044811 System and method for transferring data over a communication medium using double-buffering |
| 03/04/2004 | US20040044716 Self-timed transmission system and method for processing multiple data sets |
| 03/03/2004 | EP1393180A1 Method and apparatus for gathering queue performance data |
| 03/03/2004 | EP1093607B1 Fifo system with variable-width interface to host processor |
| 03/03/2004 | EP1032882A4 Buffering data that flows between buses operating at different frequencies |
| 03/03/2004 | CN1140869C Ring buffer and method for definition of order priority in it |
| 03/02/2004 | US6701390 FIFO buffer that can read and/or write multiple and/or selectable number of data words per bus cycle |
| 03/02/2004 | US6700825 Implementation of a multi-dimensional, low latency, first-in first-out (FIFO) buffer |
| 03/02/2004 | US6700582 Method and system for buffer management |
| 03/02/2004 | US6700409 Source synchronous I/O using temporal delay queues |
| 02/26/2004 | WO2002017494A3 Non-power-of-two grey-code counter system having binary incrementer with counts distributed with bilateral symmetry |
| 02/26/2004 | US20040039874 Method and apparatus for address FIFO for high-bandwidth command/address busses in digital storage system |
| 02/26/2004 | US20040039867 Multirate circular buffer and method of operating the same |
| 02/25/2004 | CN1478226A Low latency FIFO circuit for mixed asynchronous and synchronous systems |
| 02/25/2004 | CN1139831C Mirror shift control system for large astronomical telescope |
| 02/24/2004 | US6697927 Concurrent non-blocking FIFO array |
| 02/24/2004 | US6697923 Buffer management method and a controller thereof |
| 02/24/2004 | US6697921 Signal processor providing an increased memory access rate |
| 02/24/2004 | US6697889 First-in first-out data transfer control device having a plurality of banks |
| 02/24/2004 | US6696854 Methods and circuitry for implementing first-in first-out structure |
| 02/19/2004 | WO2003019351A3 Fifo memory devices having single data rate (sdr) and dual data rate (ddr) capability |
| 02/19/2004 | WO2002099554A3 Power controlled electronic circuit |
| 02/19/2004 | DE10232988A1 Verfahren und Vorrichtung zur getakteten Ausgabe asynchron empfangener Digitalsignale Method and apparatus for pulsed output asynchronously received digital signals |
| 02/18/2004 | CN1476232A Image processor and image processing method |
| 02/18/2004 | CN1139034C Method and apparatus for managing communication buffer of block communication data of printer |
| 02/17/2004 | US6694336 Data transfer and synchronization system |
| 02/17/2004 | US6693918 Elastic buffers for serdes word alignment and rate matching between time domains |
| 02/17/2004 | US6693567 Multi-byte Lempel-Ziv 1(LZ1) decompression |
| 02/12/2004 | WO2003060692A3 Shifting device and shifting method |
| 02/12/2004 | WO2003032147A3 Method and apparatus for buffer storage of data packets which are to be transmitted via a connection that has been set up |
| 02/12/2004 | US20040027909 Self-synchronous FIFO memory device |