| Patents for G06F 5 - Methods or arrangements for data conversion without changing the order or content of the data handled (8,116) |
|---|
| 07/13/2004 | US6762701 Scalable gray code counter and applications thereof |
| 07/08/2004 | WO2002071249A3 Method and devices for treating and/or processing data |
| 07/08/2004 | US20040133820 Interfact circuit |
| 07/08/2004 | US20040133763 Computing architecture and related system and method |
| 07/08/2004 | US20040130927 Pipeline accelerator having multiple pipeline units and related computing machine and method |
| 07/07/2004 | CN1510841A Coder, decoder and data transfer systems |
| 07/06/2004 | US6760837 Bit field processor |
| 07/06/2004 | US6760830 Modulo addressing |
| 07/06/2004 | US6760738 Exponent unit of data processing system |
| 07/01/2004 | US20040128580 Method and apparatus for flexible and programmable clock crossing control with dynamic compensation |
| 07/01/2004 | US20040128413 Low latency fifo circuits for mixed asynchronous and synchronous systems |
| 07/01/2004 | US20040125665 Low latency fifo circuit for mixed clock systems |
| 06/30/2004 | EP1433047A2 Method and apparatus for buffer storage of data packets which are to be transmitted via a connection that has been set up |
| 06/29/2004 | US6757854 Detecting faults in dual port FIFO memories |
| 06/29/2004 | US6757812 Leading bit prediction with in-parallel correction |
| 06/29/2004 | US6757758 Data transfer method, data transfer apparatus and recording apparatus |
| 06/29/2004 | US6757746 Obtaining a destination address so that a network interface device can write network data without headers directly into host memory |
| 06/29/2004 | US6757703 Associative processor addition and subtraction |
| 06/29/2004 | US6757696 Management server for synchronization system |
| 06/29/2004 | US6757348 High-speed coordinated multi-channel elastic buffer |
| 06/29/2004 | US6757292 Automatic adjustment of buffer depth for the correction of packet delay variation |
| 06/29/2004 | US6756988 Display FIFO memory management system |
| 06/24/2004 | WO2004053707A1 Method and apparatus for aligning operands for a processor |
| 06/24/2004 | WO2004053680A2 Configurable memory partitioning in hardware |
| 06/24/2004 | US20040123175 Slave QDR2 compliant coprocessor |
| 06/24/2004 | US20040122886 High-sticky calculation in pipelined fused multiply/add circuitry |
| 06/24/2004 | US20040120189 Shift register control of a circular elasticity buffer |
| 06/24/2004 | US20040119521 Adaptive frequency clock signal |
| 06/23/2004 | EP1430388A2 An apparatus and method for extracting and loading data to/from a buffer |
| 06/23/2004 | CN1507588A Method and apparatus for gathering queue performance data |
| 06/22/2004 | US6754795 Methods and apparatus for forming linked list queue using chunk-based structure |
| 06/22/2004 | US6754777 FIFO memory devices and methods of operating FIFO memory devices having multi-port cache memory devices therein |
| 06/22/2004 | US6754743 Virtual insertion of cells from a secondary source into a FIFO |
| 06/22/2004 | US6754740 Interface apparatus for connecting devices operating at different clock rates, and a method of operating the interface |
| 06/22/2004 | US6754688 Method and apparatus to calculate the difference of two numbers |
| 06/22/2004 | US6754685 Dynamic popcount/shift circuit |
| 06/22/2004 | CA2192161C Two stage clock dejitter circuit for regenerating an e4 telecommunications signal from the data component of an sts-3c signal |
| 06/17/2004 | WO2004051492A1 Storage device for compressing the same input value |
| 06/17/2004 | US20040117584 Method and apparatus for assembling non-aligned packet fragments over multiple cycles |
| 06/17/2004 | US20040113822 Scalable gray code counter and applications thereof |
| 06/17/2004 | US20040113650 Methods and apparatuses for signal line termination |
| 06/16/2004 | EP1429244A1 Compiler |
| 06/16/2004 | CN1505779A Method and device for adapting the data rate of a data stream |
| 06/10/2004 | US20040111542 Extending circuit for memory and transmitting-receiving device using extending circuit for memory |
| 06/10/2004 | US20040111540 Configurably prefetching head-of-queue from ring buffers |
| 06/10/2004 | US20040111535 Intelligent network interface system and method for accelerated protocol processing |
| 06/10/2004 | US20040108945 Encoder, decoder, and data transfer system |
| 06/09/2004 | EP1425656A1 Buffer system with sequential and non-sequential block access |
| 06/08/2004 | US6748039 System and method for synchronizing a skip pattern and initializing a clock forwarding interface in a multiple-clock system |
| 06/08/2004 | US6747582 Data compressing apparatus, reconstructing apparatus, and its method |
| 06/03/2004 | WO2003090063A3 Output rate change |
| 06/02/2004 | CN1152332C Method and device for schedule display |
| 06/01/2004 | US6745314 Circular buffer control circuit and method of operation thereof |
| 06/01/2004 | US6745265 Method and apparatus for generating status flags in a memory device |
| 06/01/2004 | US6745216 Shift register allowing direct data insertion |
| 06/01/2004 | US6744837 Clock switching circuit |
| 06/01/2004 | US6744833 Data resynchronization between modules sharing a common clock |
| 05/27/2004 | WO2004044731A2 Device and method for performing shift/rotate operations |
| 05/27/2004 | US20040102927 Enhanced preventative maintenance system and method of use |
| 05/25/2004 | US6742110 Preventing the execution of a set of instructions in parallel based on an indication that the instructions were erroneously pre-coded for parallel execution |
| 05/25/2004 | US6742061 Accessory control interface |
| 05/25/2004 | US6742018 System and method for storing and retrieving data by keywords converted into divided long integers |
| 05/25/2004 | US6741193 Parallel in serial out circuit having flip-flop latching at multiple clock rates |
| 05/21/2004 | WO2004042591A1 Data processing apparatus with address redirection in response to periodic address patterns |
| 05/21/2004 | WO2004042552A1 Declarative markup for scoring multiple time-based assets and events within a scene composition system |
| 05/21/2004 | WO2004019202A3 Fifo clock domain change |
| 05/21/2004 | WO2003044652A3 High-speed first-in-first-out buffer |
| 05/21/2004 | WO2003029953A3 Method for storing or transferring data |
| 05/20/2004 | US20040098654 FIFO memory with ECC function |
| 05/20/2004 | US20040098441 System, method, and apparatus for division coupled with truncation of signed binary numbers |
| 05/20/2004 | US20040095355 Computer chipsets having data reordering mechanism |
| 05/20/2004 | US20040095354 Declarative markup for scoring multiple time-based assets and events within a scene composition system |
| 05/19/2004 | EP1419433A2 Fifo memory devices having single data rate (sdr) and dual data rate (ddr) capability |
| 05/19/2004 | DE19806299B4 Normalisierungsschaltung für eine Fließkomma-Berechnungseinrichtung Normalization circuit for a floating-point calculation means |
| 05/19/2004 | CN1497971A Extended time code for multimedium reproducing |
| 05/19/2004 | CN1497440A Time reference of multimedium object |
| 05/18/2004 | US6738795 Self-timed transmission system and method for processing multiple data sets |
| 05/18/2004 | US6738789 Data package including synchronization data |
| 05/18/2004 | US6737997 Data conversion apparatus and data conversion method |
| 05/13/2004 | US20040093440 Device and method for controlling a stream of data packets |
| 05/12/2004 | EP1086416B1 An interface apparatus for connecting devices operating at different clock rates, and a method of operating the interface |
| 05/12/2004 | CN1496068A Asynchronous receiving digital signal clock cutput method and device |
| 05/12/2004 | CN1149780C Descrambling device of security element and security element comprising such device |
| 05/12/2004 | CN1149483C Method for controlling digital buffer with controller in digital buffer storage |
| 05/12/2004 | CN1149469C Processor for supporting packed data |
| 05/11/2004 | US6735223 Method of controlling offset of time stamp and apparatus for transmitting packet using the same |
| 05/11/2004 | US6734813 Data receiving device for receiving serial data according to over-sampling |
| 05/06/2004 | WO2002097620A3 Safe application distribution and execution in a wireless environment |
| 05/06/2004 | US20040088596 Method and apparatus for synchronous loading and out-of-phase unloading of data registers |
| 05/06/2004 | EP1416639A1 Analog-to-digital converter with on-chip memory |
| 05/06/2004 | EP1416385A2 Parallel efficiency calculation method and apparatus |
| 05/06/2004 | EP1416373A2 Method and apparatus to reduce access time in synchronous fifos with zero latency overhead |
| 05/05/2004 | CN1494767A Method for compressing/decompressing structured document |
| 05/05/2004 | CN1493969A Storage table renewing method |
| 05/04/2004 | US6732223 Method and apparatus for address FIFO for high-bandwidth command/address busses in digital storage system |
| 05/04/2004 | US6732213 Multiple processor computer |
| 05/04/2004 | US6732205 Serial/parallel conversion circuit, data transfer control device, and electronic equipment |
| 05/04/2004 | US6732204 Data transfer control device and electronic equipment |
| 05/04/2004 | US6732200 Absorbing jitter during data transmission between applications operating at different frequencies |
| 05/04/2004 | US6732134 Handler for floating-point denormalized numbers |