Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
Patents for H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof (218,143)
11/2003
11/18/2003US6649453 Contactless uniform-tunneling separate p-well (CUSP) non-volatile memory array architecture, fabrication and operation
11/18/2003US6649442 Fast line dump structure for solid state image sensor
11/18/2003US6649430 Characteristic evaluation apparatus for insulated gate type transistors
11/18/2003US6649032 System and method for sputtering silicon films using hydrogen gas mixtures
11/18/2003US6647795 Capacitive physical load sensor and detection system
11/18/2003US6647794 Absolute pressure sensor
11/13/2003WO2003094257A1 Silicon particles used as additives for improving the charge carrier mobility in organic semiconductors
11/13/2003WO2003094245A1 Heterojunction p-i-n diode and method of making the same
11/13/2003WO2003094244A1 Electronic devices comprising bottom-gate tfts and their manufacture
11/13/2003WO2003094243A1 Metal gate electrode using silicidation and method of formation thereof
11/13/2003WO2003094242A1 Esd-robust power switch and method of using same
11/13/2003WO2003094241A1 Esd-robust power switch and method of using same
11/13/2003WO2003094240A1 High voltage switching devices and process for forming same
11/13/2003WO2003094239A1 Semiconductor device having strained silicon and silicon germanium alloy layers
11/13/2003WO2003094238A1 Integrating device
11/13/2003WO2003094237A1 Line element and method of manufacturing the line element
11/13/2003WO2003094219A1 Method of making transistors
11/13/2003WO2003094204A2 Short channel trench power mosfet with low threshold voltage
11/13/2003WO2003094200A2 Low voltage high density trench-gated power device with uniformly doped channel and its edge termination technique
11/13/2003WO2003067665A3 Cellular mosfet devices and their manufacture
11/13/2003WO2003065437A3 Method for forming high quality oxide layers of different thickness in one processing step
11/13/2003WO2003058683A3 Method for fabricating a high voltage power mosfet having a voltage sustaining region that includes doped columns formed by rapid diffusion
11/13/2003WO2003050883A3 Silicon on insulator device and method of making the same
11/13/2003WO2003042721A3 Trilayered beam mems device and related methods
11/13/2003WO2003038873A3 Removing an amorphous oxide from a monocrystalline surface
11/13/2003WO2003028106A3 Rf circuits including transistors having strained material layers
11/13/2003WO2003019693A3 Solutions of organic semiconductors
11/13/2003WO2002065516A3 Improved process for deposition of semiconductor films
11/13/2003US20030212853 Adaptive processor architecture incorporating a field programmable gate array control element having at least one embedded microprocessor core
11/13/2003US20030212725 Methods of factoring and modular arithmetic
11/13/2003US20030212724 Methods of computing with digital multistate phase change materials
11/13/2003US20030212225 Polymerization of olefins
11/13/2003US20030211741 Dielectric thin film, method for making the same and electric components thereof
11/13/2003US20030211733 Graded/stepped silicide process to improve mos transistor
11/13/2003US20030211732 High-resistivity metal in a phase-change memory cell
11/13/2003US20030211724 Providing electrical conductivity between an active region and a conductive layer in a semiconductor device using carbon nanotubes
11/13/2003US20030211718 MIS field effect transistor and method of manufacturing the same
11/13/2003US20030211716 Semiconductor device and method for fabricating the same
11/13/2003US20030211713 Semiconductor device and method for manufacturing
11/13/2003US20030211710 Method of manufacturing III-V group compound semiconductor
11/13/2003US20030211707 Method and system for dicing wafers, and semiconductor structures incorporating the products thereof
11/13/2003US20030211704 Thermally stable crystalline defect-free germanium bonded to silicon and silicon dioxide
11/13/2003US20030211697 Multiple etch method for fabricating spacer layers
11/13/2003US20030211696 Semiconductor device and fabrication method thereof
11/13/2003US20030211694 Semiconductor device and method for manufacturing the same
11/13/2003US20030211693 Semiconductor device and method for manufacturing the same
11/13/2003US20030211691 Method for manufacturing semiconductor devices
11/13/2003US20030211689 Nonvolatile memory device with a non-planar gate-insulating layer and method of fabricating the same
11/13/2003US20030211688 Method of forming poly tip of floating gate in split-gate memory
11/13/2003US20030211684 Gate stack for high performance sub-micron CMOS devices
11/13/2003US20030211683 Minimizing a size of the device isolation region, maximizing a size of the active regions; high integration
11/13/2003US20030211682 Method for fabricating a gate electrode
11/13/2003US20030211681 Fully-depleted SOI MOSFETs with low source and drain resistance and minimal overlap capacitance using a recessed channel damascene gate process
11/13/2003US20030211680 Interfacial layer for gate electrode and high-k dielectric layer and methods of fabrication
11/13/2003US20030211672 Method of improving quality of interface between gate and gate oxide
11/13/2003US20030211671 Array of discrete tiles formed above common drain region; gate metallization layer; varied in both the x-axis and the y- axis by predetermined increments; bonding pads
11/13/2003US20030211669 Semiconductor device and method of manufacturing the same
11/13/2003US20030211668 Method of fabricating thin film transistor
11/13/2003US20030211667 Method of fabricating thin film transistor
11/13/2003US20030211666 Thin-film transistor and method for manufacturing same
11/13/2003US20030211664 Semiconductor device and method of manufacturing the same
11/13/2003US20030211663 Body-tied silicon on insulator semiconductor device and method therefor
11/13/2003US20030211662 Semiconductor device with semiconductor circuit comprising semiconductor units, and method for fabricating it
11/13/2003US20030211660 BOC BGA package for die with I-shaped bond pad layout
11/13/2003US20030211659 BOC BGA package for die with I-shaped bond pad layout
11/13/2003US20030211642 Protective side wall passivation for VCSEL chips
11/13/2003US20030210586 Magnetic storage apparatus having dummy magnetoresistive effect element and manufacturing method thereof
11/13/2003US20030210582 Semiconductor memory device having a side wall insulation film
11/13/2003US20030210573 Electrically erasable charge trap nonvolatile memory cells having erase threshold voltage that is higher than an initial threshold voltage, and methods of erasing and designing same
11/13/2003US20030210511 Capacitive device
11/13/2003US20030210357 Contact structure
11/13/2003US20030210218 Liquid-crystal display apparatus capable of reducing line crawling
11/13/2003US20030210089 Boosted voltage generating circuit and semiconductor memory device having the same
11/13/2003US20030209990 EL element drive circuit and display panel
11/13/2003US20030209971 Programmable structure, an array including the structure, and methods of forming the same
11/13/2003US20030209816 Semiconductor device and method of manufacturing the same
11/13/2003US20030209811 Semiconductor device and method of formation
11/13/2003US20030209792 Spherical shaped semiconductor device, a flexible printed wiring substrate, and mounting method thereof
11/13/2003US20030209791 Semiconductor structure having stacked semiconductor devices
11/13/2003US20030209782 Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction
11/13/2003US20030209781 Semiconductor power device
11/13/2003US20030209780 Device including a resistive path to introduce an equivalent RC circuit
11/13/2003US20030209774 Voltage with standing structure for a semiconductor device
11/13/2003US20030209772 Integrated circuits; connecting contactor pads; protective coatings
11/13/2003US20030209770 Unipolar spin transistor and the applications of the same
11/13/2003US20030209767 Forming channels; diffusion of impurities; forming silicide
11/13/2003US20030209766 Method for using a surface geometry for a MOS-gated device in the manufacture of dice having different sizes
11/13/2003US20030209765 All-in-one disposable/permanent spacer elevated source/drain, self-aligned silicide CMOS
11/13/2003US20030209763 Semiconductor device and method for fabricating the same
11/13/2003US20030209762 Semiconductor device and method for fabricating the same
11/13/2003US20030209761 Semiconductor device and manufacturing method thereof
11/13/2003US20030209759 Mosfet device having geometry that permits frequent body contact
11/13/2003US20030209758 Transistor of semiconductor device, and method for forming the same
11/13/2003US20030209757 Semiconductor component with an increased breakdown voltage in the edge area
11/13/2003US20030209756 Semiconductor memory reducing current consumption and narrow channel effect and method of manufacturing the same
11/13/2003US20030209755 Vertical split gate flash memory cell and method for fabricating the same
11/13/2003US20030209754 Two bit non-volatile electrically erasable and programmable memory structure, a process for producing said memory structure and methods for programming, reading and erasing said memory structure
11/13/2003US20030209753 Nonvolatile semiconductor memory device and method for manufacturing the same
11/13/2003US20030209752 EEPROM device with substrate hot-electron injector for low-power
11/13/2003US20030209750 Semiconductor layer with laterally variable doping, and method for producing it
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