Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
03/1998
03/17/1998US5728628 Two-step metal etch process for selective gap fill of submicron inter-connects and structure for same
03/17/1998US5728627 Methods of forming planarized conductive interconnects for integrated circuits
03/17/1998US5728626 Spin-on conductor process for integrated circuits
03/17/1998US5728625 Process for device fabrication in which a thin layer of cobalt silicide is formed
03/17/1998US5728624 Bonded wafer processing
03/17/1998US5728623 Method of bonding a III-V group compound semiconductor layer on a silicon substrate
03/17/1998US5728622 Process for forming field oxide layers in semiconductor devices
03/17/1998US5728621 Method for shallow trench isolation
03/17/1998US5728620 Isolation method of semiconductor device
03/17/1998US5728619 Selective reactive Ion etch (RIE) method for forming a narrow line-width high aspect ratio via through an integrated circuit layer
03/17/1998US5728618 Method to fabricate large capacitance capacitor in a semiconductor circuit
03/17/1998US5728617 Method for fabricating vertical walled stacked capacitors for dram cells
03/17/1998US5728616 Method of making a semiconductor memory device with improved capacitor
03/17/1998US5728615 Method of manufacturing a polysilicon resistor having uniform resistance
03/17/1998US5728614 Method to improve the topography of a field oxide region
03/17/1998US5728613 Method of using an insulator spacer to form a narrow base width lateral bipolar junction transistor
03/17/1998US5728611 Method of fabricating semiconductor device
03/17/1998US5728610 Method for producing a thin film transistor having improved carrier mobility characteristics and leakage current characteristics
03/17/1998US5728609 Method for producing contact holes
03/17/1998US5728608 Sulfur hexafluoride and chlorine
03/17/1998US5728607 Method of making a P-channel bipolar transistor
03/17/1998US5728606 Electronic Package
03/17/1998US5728604 Method for making thin film transistors
03/17/1998US5728603 Method of forming a crystalline ferroelectric dielectric material for an integrated circuit
03/17/1998US5728600 Circuit encapsulation process
03/17/1998US5728599 Printable superconductive leadframes for semiconductor device assembly
03/17/1998US5728598 Method of manufacturing a SRAM cell having a low stand-by current
03/17/1998US5728597 Method for forming a capacitor in a semiconductor device
03/17/1998US5728596 Method for forming a semiconductor buried contact with a removable spacer
03/17/1998US5728595 Method of fabricating a self-aligned contact hole for a semiconductor device
03/17/1998US5728594 Method of making a multiple transistor integrated circuit with thick copper interconnect
03/17/1998US5728593 Power insulated-gate transistor having three terminals and a manufacturing method thereof
03/17/1998US5728592 Method for fabricating a thin film transistor matrix device
03/17/1998US5728591 Process for manufacturing light valve device using semiconductive composite substrate
03/17/1998US5728507 Method for planarizing a semiconductor layer
03/17/1998US5728506 Lithographic processes employing radiation sensitive polymers and photosensitive acid generators
03/17/1998US5728504 Positive photoresist compositions and multilayer resist materials using the same
03/17/1998US5728495 Scanning exposure method and apparatus
03/17/1998US5728492 Mask for projection system using charged particle beam
03/17/1998US5728491 Chrome film on silica substrate, integrated circuits
03/17/1998US5728470 Multi-layer wiring substrate, and process for producing the same
03/17/1998US5728453 Method of fabricating topside structure of a semiconductor device
03/17/1998US5728425 Method for chemical vapor deposition of semiconductor films by separate feeding of source gases and growing of films
03/17/1998US5728421 Forming a template layer by vapor deposition on substrate, depositing ferrite on annealed template
03/17/1998US5728308 Method of polishing a semiconductor substrate during production of a semiconductor device
03/17/1998US5728278 Plasma processing apparatus
03/17/1998US5728276 Treatment apparatus
03/17/1998US5728261 Magnetically enhanced radio frequency reactive ion etching method and apparatus
03/17/1998US5728260 Distributors, conduits, focusing collar, lips, coverings
03/17/1998US5728259 Process for fabricating thin-film semiconductor device without plasma induced damage
03/17/1998US5728254 Ceramic ring for guiding a wafer down to the lower electrode of a dry etcher
03/17/1998US5728248 Method for making a multi-tier laminate substrate with internal heat spreader
03/17/1998US5728247 Method for mounting a circuit
03/17/1998US5728223 Reactant gas ejector head and thin-film vapor deposition apparatus
03/17/1998US5728222 Apparatus for chemical vapor deposition of aluminum oxide
03/17/1998US5728215 Method for forming a film by selective area MOCVD growth
03/17/1998US5728214 Surface treatment of an oxide LNBA2CU307-X single crystal
03/17/1998US5728211 Silicon single crystal with low defect density and method of producing same
03/17/1998US5727990 Method for mirror-polishing chamfered portion of wafer and mirror-polishing apparatus
03/17/1998US5727917 Magazine conveying device
03/17/1998US5727727 Flowing solder in a gap
03/17/1998US5727685 Reticle container with corner holding
03/17/1998US5727578 Apparatus for the treatment and drying of semiconductor wafers in a fluid
03/17/1998US5727332 Contamination control in substrate processing system
03/12/1998WO1998010628A1 Carrier element(1) for a semi-conductor chip
03/12/1998WO1998010625A1 An integrated circuit package
03/12/1998WO1998010470A1 Asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region
03/12/1998WO1998010468A1 Static induction transistors
03/12/1998WO1998010465A1 Connecting structure of semiconductor element, liquid crystal display device using the structure, and electronic equipment using the display device
03/12/1998WO1998010464A1 A novel process for reliable ultra-thin oxynitride formation
03/12/1998WO1998010463A1 Germanes and doping with germanes
03/12/1998WO1998010423A1 Giant magnetoresistive effect memory cell
03/12/1998WO1998010335A1 Alkysulfonyloximes for high-resolution i-line photoresists of high sensitivity
03/12/1998WO1998010050A1 Non-corrosive cleaning composition for removing plasma etching residues
03/12/1998WO1998009804A1 Flattening process for bonded semiconductor substrates
03/12/1998WO1998009731A1 Method and apparatus for controlled particle deposition on surfaces
03/12/1998WO1998002923A3 Depletion region stopper for pn junction in silicon carbide
03/12/1998WO1997049134A3 Soi-transistor circuitry employing soi-transistors and method of manufacture thereof
03/12/1998WO1997043656A3 Wafer-level burn-in and test
03/12/1998DE19738184A1 Production of organic thin films on substrate
03/12/1998DE19738118A1 Semiconductor device mounting on circuit board
03/12/1998DE19737825A1 Verfahren zur Herstellung einer Beschichtung A process for preparing a coating
03/12/1998DE19724487A1 Input buffer protection circuit for integrated semiconductor circuit, e.g. CMOS gate array
03/12/1998DE19724472A1 Wiring layout for semiconductor component, e.g. bit-line of DRAM
03/12/1998DE19721448A1 Semiconductor module, e.g. MMIC gallium arsenide integrated circuit
03/12/1998DE19719179A1 Semiconductor module, e.g. LSI circuit, with air bridge wiring
03/12/1998DE19715730A1 Semiconductor component, e.g. integrated circuit, on semiconductor substrate manufacture
03/12/1998DE19710688A1 Conductive plug manufacture
03/12/1998DE19710233A1 Semiconductor device, e.g. MOS transistor with CMOS structure
03/12/1998DE19708259A1 Semiconductor device with memory cell and peripheral circuit parts
03/12/1998DE19708019A1 Bipolar integrated semiconductor circuit with cross-polarity connection protection
03/12/1998DE19652548C1 Continuous epitaxy of nitrogen-containing semiconductor layers
03/12/1998DE19640273C1 Verfahren zur Herstellung barrierenfreier Halbleiterspeicheranordnungen A process for preparing barrier-free semiconductor memory devices
03/12/1998DE19636956A1 Groove filling method for shallow trench isolation of semiconductor ROM
03/12/1998DE19636914A1 Void-free trench filling process
03/12/1998DE19636756A1 Multilayer technology inductance components mfr
03/12/1998DE19636193A1 Crystal quality determination method for semiconductor and solid state material
03/12/1998DE19636112A1 Carrier element for semiconductor chip
03/12/1998DE19636055A1 Edge material removing machining method for semiconductor wafer
03/12/1998DE19635072A1 Method for measuring roughness of semiconductor or other surface