Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
06/1999
06/16/1999CN1043614C Method and apparatus for drying of polymer protective layer which has been applyed with solution on surface of articles
06/15/1999US5913150 Method for manufacturing semiconductor device using spin on glass layer
06/15/1999US5913149 Method for fabricating stacked layer silicon nitride for low leakage and high capacitance
06/15/1999US5913148 Reduced size etching method for integrated circuits
06/15/1999US5913147 Method for fabricating copper-aluminum metallization
06/15/1999US5913146 Semiconductor device having aluminum contacts or vias and method of manufacture therefor
06/15/1999US5913145 Forming titanium layer on patterned substrate, forming layer of tungsten nitride on titanium layer, annealing to form titanium nitride and tungsten
06/15/1999US5913144 Oxidized diffusion barrier surface for the adherence of copper and method for same
06/15/1999US5913143 Method of making a multilayer interconnection of semiconductor device using plug
06/15/1999US5913142 Method of improving the planarizaton of an inter-metal dielectric layer
06/15/1999US5913141 Reliable interconnect via structures and methods for making the same
06/15/1999US5913140 Method for reduction of plasma charging damage during chemical vapor deposition
06/15/1999US5913139 Method of manufacturing a semiconductor device with local interconnect of metal silicide
06/15/1999US5913138 Method of manufacturing an antifuse element having a controlled thickness
06/15/1999US5913136 Process for making a transistor with self-aligned source and drain contacts
06/15/1999US5913135 Method for forming planar field effect transistors with source and drain on oxide and device constructed therefrom
06/15/1999US5913133 Method of forming isolation layer for semiconductor device
06/15/1999US5913132 Method of forming a shallow trench isolation region
06/15/1999US5913131 Alternative process for BPTEOS/BPSG layer formation
06/15/1999US5913130 Method for fabricating a power device
06/15/1999US5913129 Method of fabricating a capacitor structure for a dynamic random access memory
06/15/1999US5913128 Method for forming texturized polysilicon
06/15/1999US5913127 Method to thermally form hemispherical grain (HSG) silicon to enhance capacitance for application in high density DRAMS
06/15/1999US5913126 Methods of forming capacitors including expanded contact holes
06/15/1999US5913125 Method of controlling stress in a film
06/15/1999US5913124 Method of making a self-aligned silicide
06/15/1999US5913123 Manufacturing method for deep-submicron P-type metal-oxide semiconductor shallow junction
06/15/1999US5913122 Method of making high breakdown voltage twin well device with source/drain regions widely spaced from FOX regions
06/15/1999US5913121 Method of making a self-aligning type contact hole for a semiconductor device
06/15/1999US5913120 Process for fabricating integrated devices including nonvolatile memories and transistors with tunnel oxide protection
06/15/1999US5913119 Method of selective growth of a hemispherical grain silicon layer on the outer sides of a crown shaped DRAM capacitor structure
06/15/1999US5913118 In a semiconductor substrate
06/15/1999US5913117 Method for manufacturing ferroelectric capacitor
06/15/1999US5913116 Method of manufacturing an active region of a semiconductor by diffusing a dopant out of a sidewall spacer
06/15/1999US5913115 Method for producing a CMOS circuit
06/15/1999US5913114 Method of manufacturing a semiconductor device
06/15/1999US5913113 Method for fabricating a thin film transistor of a liquid crystal display device
06/15/1999US5913112 Method of manufacturing an insulated gate field effect semiconductor device having an offset region and/or lightly doped region
06/15/1999US5913111 Method of manufacturing an insulaed gate transistor
06/15/1999US5913110 Method for producing a plastic material composite component, a plastic material composite component and a mold for injection molding same
06/15/1999US5913109 Fixtures and methods for lead bonding and deformation
06/15/1999US5913107 Photosemiconductor device and method of fabricating the same
06/15/1999US5913105 Method and system for recognizing scratch patterns on semiconductor wafers
06/15/1999US5913104 Method and apparatus to hold integrated circuit chips onto a chuck and to simultaneously remove multiple integrated circuit chips from a cutting chuck
06/15/1999US5913103 Method of detecting metal contaminants in a wet chemical using enhanced semiconductor growth phenomena
06/15/1999US5913102 Method for forming patterned photoresist layers with enhanced critical dimension uniformity
06/15/1999US5913101 Semiconductor device manufacturing method by carrying out logic design
06/15/1999US5913100 Mo-W material for formation of wiring, Mo-W target and method for production thereof, and Mo-W wiring thin film
06/15/1999US5912843 Scalable flash EEPROM memory cell, method of manufacturing and operation thereof
06/15/1999US5912842 Nonvolatile PMOS two transistor memory cell and array
06/15/1999US5912836 Circuit for detecting both charge gain and charge loss properties in a non-volatile memory array
06/15/1999US5912835 Non-volatile ferroelectric memory device for storing data bits restored upon power-on and intermittently refreshed
06/15/1999US5912824 Ion implantation simulation method
06/15/1999US5912797 Tin and titanium oxide with zirconium oxide or hafnium oxide
06/15/1999US5912796 Metallized film capacitor and manufacturing process
06/15/1999US5912727 Projection exposure method in which mask patterns are imaged on photosensitive substrates with adjustment of illumination and projection parameters corresponding to the mask pattern
06/15/1999US5912726 Projection exposure apparatus and method having a positional deviation detection system that employs light from an exposure illumination system
06/15/1999US5912725 Illumination optical system to be used in an exposure apparatus and a method of manufacturing a semiconductor structure using the exposure apparatus
06/15/1999US5912618 System for detecting the presence of an electrically conductive object, particularly an integrated circuit on a chip card
06/15/1999US5912591 Oscillator circuit and delay circuit
06/15/1999US5912581 Spurious-emission-reducing terminal configuration for an integrated circuit
06/15/1999US5912510 Bonding structure for an electronic device
06/15/1999US5912509 MOS semiconductor device and method of manufacturing the same
06/15/1999US5912508 Metal-semiconductor contact formed using nitrogen plasma
06/15/1999US5912505 Semiconductor package and semiconductor device
06/15/1999US5912502 Wafer having a plurality of IC chips having different sizes formed thereon
06/15/1999US5912500 Integrated photocathode
06/15/1999US5912498 Article comprising an oxide layer on GAN
06/15/1999US5912497 Insulated gate bipolar transistor
06/15/1999US5912496 Semiconductor device having power MOS transistor including parasitic transistor
06/15/1999US5912495 For an inductive load
06/15/1999US5912493 Enhanced oxidation for spacer formation integrated with LDD implantation
06/15/1999US5912492 Integrated circuit structure incorporating a metal oxide semiconductor field effect transistor (MOSFET) having improved hot carrier immunity
06/15/1999US5912491 MOS device
06/15/1999US5912489 Dual source side polysilicon select gate structure utilizing single tunnel oxide for NAND array flash memory
06/15/1999US5912488 Stacked-gate flash EEPROM memory devices having mid-channel injection characteristics for high speed programming
06/15/1999US5912487 Split gate flash EEPROM memory cell structure
06/15/1999US5912486 Germanium
06/15/1999US5912485 Capacitor structure for a semiconductor memory device
06/15/1999US5912483 Output circuit provided with source follower circuit having depletion type MOS transistor
06/15/1999US5912481 Heterojunction bipolar transistor having wide bandgap, low interdiffusion base-emitter junction
06/15/1999US5912480 Heterojunction semiconductor device
06/15/1999US5912479 Heterojunction bipolar semiconductor device
06/15/1999US5912477 High efficiency light emitting diodes
06/15/1999US5912476 Compound semiconductor epitaxial wafer
06/15/1999US5912474 Thin film integrated circuit including at least two P-type transistors
06/15/1999US5912473 Oligothiophene compound and polytetrafluoroethylene oriented film, polyphenylene vinylene
06/15/1999US5912468 Charged particle beam exposure system
06/15/1999US5912467 Charged particle beam exposure apparatus
06/15/1999US5912282 Die attach adhesive compositions
06/15/1999US5912188 Method of forming a contact hole in an interlevel dielectric layer using dual etch stops
06/15/1999US5912187 Method of fabricating circuits
06/15/1999US5912186 Supplying heated etching gases while applying laser to activate etching gas
06/15/1999US5912185 Methods for forming contact holes having improved sidewall profiles
06/15/1999US5912096 Accuracy
06/15/1999US5912095 Mask substrate manufacturing methods
06/15/1999US5912068 Epitaxial oxides on amorphous SiO2 on single crystal silicon
06/15/1999US5912054 Coating method and apparatus
06/15/1999US5912049 Process liquid dispense method and apparatus
06/15/1999US5912047 Borosilicate electronic coatings
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