Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
06/1999
06/30/1999CN1221313A Method for manufacture a certain equipment containing a printed-circuit board
06/30/1999CN1221310A Tape automated bonding film
06/30/1999CN1221309A Terminal electrode for circuit substrate on which chip pachage mounted and method for manufacturing the same
06/30/1999CN1221223A Semiconductor device and manufacturing method for the same
06/30/1999CN1221222A EEPROM device and manufacture method thereof
06/30/1999CN1221221A Method of forming semiconductor device
06/30/1999CN1221220A Semiconductor device comprising capacitor and method of fabricating the same
06/30/1999CN1221219A 半导体器件 Semiconductor devices
06/30/1999CN1221218A Semiconductor substrate and thin film semiconductor device, method of manufacturing the same, and anodizing apparatus
06/30/1999CN1221217A Output buffer circuit having variable output impedance
06/30/1999CN1221214A Semiconductor device manufacturing method
06/30/1999CN1221213A Semiconductor integrated circuit and method for manufacturing the same and semiconductor device and method for manufacturing the same
06/30/1999CN1221212A Method for controlling thicknesses of layers formed by deposition equipment for processing semiconductors
06/30/1999CN1221211A Improved gapfill of semiconductor structure using doped silicate glasses
06/30/1999CN1221210A Method for producing vias having variable sidewall profile
06/30/1999CN1221209A Method of implementing electron beam lithography using uniquely positioned alignment marks and wafer with such alignment marks
06/30/1999CN1221208A Method for forming fine inter-pattern space in semiconductor device
06/30/1999CN1221207A Substrate processing method and apparatus and SOI substrate
06/30/1999CN1221206A Level conversion circuit and semiconductor integrated circuit device employing level conversion circuit
06/30/1999CN1221205A Semiconductor substrate and thin-film semiconductive member, and method for making thereof
06/30/1999CN1221128A Development system for manufacturing semiconductor device and controlling method thereof
06/30/1999CN1221124A Semiconductor display device, correcting system and correcting method of semiconductor display device
06/30/1999CN1221112A Test and burn-in apparatus in-line system using apparatus, and test method using the system
06/30/1999CN1221090A Device for distributing working gas and installation for supplying working gas that is equipment with such device
06/29/1999US5918152 Gap filling method using high pressure
06/29/1999US5918151 Method of manufacturing a semiconductor substrate and an apparatus for manufacturing the same
06/29/1999US5918150 Method for a chemical vapor deposition of copper on an ion prepared conductive surface
06/29/1999US5918149 Fabricating a semiconductor structure on a wafer
06/29/1999US5918148 Method for manufacturing semiconductor device
06/29/1999US5918147 Process for forming a semiconductor device with an antireflective layer
06/29/1999US5918146 Method of manufacturing semiconductor device having multilayer wiring structure, with improved version of step of forming interlayer dielectric layer
06/29/1999US5918145 Method of forming a microelectronic device incorporating low resistivity straps between regions
06/29/1999US5918144 Method of manufacturing a semiconductor device
06/29/1999US5918143 Fabricating a sub-micron structure of etch-resistant metal/semiconductor compound on a substrate of semiconductor material
06/29/1999US5918142 Method for fabricating a semiconductor device
06/29/1999US5918141 Method of masking silicide deposition utilizing a photoresist mask
06/29/1999US5918140 Semiconductor doping process which enhances the dopant incorporation achievable using the gas immersion laser doping technique
06/29/1999US5918139 Method of manufacturing a bonding substrate
06/29/1999US5918136 SOI substrate and method of producing the same
06/29/1999US5918135 Methods for forming integrated circuit capacitors including dual electrode depositions
06/29/1999US5918134 Method of reducing transistor channel length with oxidation inhibiting spacers
06/29/1999US5918133 Semiconductor device having dual gate dielectric thickness along the channel and fabrication thereof
06/29/1999US5918132 Method for narrow space formation and self-aligned channel implant
06/29/1999US5918131 Method of manufacturing a shallow trench isolation structure
06/29/1999US5918130 Transistor fabrication employing formation of silicide across source and drain regions prior to formation of the gate conductor
06/29/1999US5918129 For doping an integrated circuit device channel in a semiconductor substrate
06/29/1999US5918128 Reduced channel length for a high performance CMOS transistor
06/29/1999US5918127 Method of enhancing electrostatic discharge (ESD) protection capability in integrated circuits
06/29/1999US5918126 Method of fabricating an integrated circuit having devices arranged with different device densities using a bias differential to form devices with a uniform size
06/29/1999US5918125 Process for manufacturing a dual floating gate oxide flash memory cell
06/29/1999US5918124 Fabrication process for a novel multi-storage EEPROM cell
06/29/1999US5918123 Method for fabricating capacitor of semiconductor device
06/29/1999US5918122 Methods of forming integrated circuitry, DRAM cells and capacitors
06/29/1999US5918121 Method of reducing substrate losses in inductor
06/29/1999US5918120 Method for fabricating capacitor-over-bit line (COB) dynamic random access memory (DRAM) using tungsten landing plug contacts and Ti/TiN bit lines
06/29/1999US5918119 Process for integrating MOSFET devices, comprised of different gate insulator thicknesses, with a capacitor structure
06/29/1999US5918118 Dual deposition methods for forming contact metallizations, capacitors, and memory devices
06/29/1999US5918117 Method for manufacturing semiconductor device having an ESD protection region
06/29/1999US5918116 Process for forming gate oxides possessing different thicknesses on a semiconductor substrate
06/29/1999US5918114 Method of forming vertical trench-gate semiconductor devices having self-aligned source and body regions
06/29/1999US5918113 Process for producing a semiconductor device using anisotropic conductive adhesive
06/29/1999US5918107 Method and system for fabricating and testing assemblies containing wire bonded semiconductor dice
06/29/1999US5918036 Computer implemented simulation method
06/29/1999US5917879 Reflective reduction imaging optical system for X-ray lithography
06/29/1999US5917765 Semiconductor memory device capable of burn in mode operation
06/29/1999US5917756 Nonvolatile semiconductor memory cell capable of saving overwritten cell and its saving method
06/29/1999US5917751 Nonvolatile semiconductor memory device
06/29/1999US5917744 Semiconductor memory having hierarchical bit line architecture with interleaved master bitlines
06/29/1999US5917729 Method of and apparatus for placing and routing elements of semiconductor integrated circuit having reduced delay time
06/29/1999US5917707 Flexible contact structure with an electrically conductive shell
06/29/1999US5917604 Alignment device and lithographic apparatus provided with such a device
06/29/1999US5917581 Projection exposure method and apparatus therefor
06/29/1999US5917579 Block exposure of semiconductor wafer
06/29/1999US5917342 On a semiconductor substrate
06/29/1999US5917333 Semiconductor integrated circuit device with diagnostic circuit using resistor
06/29/1999US5917294 Synchronization control apparatus and method
06/29/1999US5917247 Static type memory cell structure with parasitic capacitor
06/29/1999US5917246 Semiconductor package with pocket for sealing material
06/29/1999US5917244 Integrated circuit inductor structure formed employing copper containing conductor winding layer clad with nickel containing conductor layer
06/29/1999US5917241 High frequency semiconductor device having source, drain, and gate leads
06/29/1999US5917237 Semiconductor integrated circuit device and lead frame therefor
06/29/1999US5917235 Semiconductor device having LOC structure, a semiconductor device lead frame, TAB leads, and an insulating TAB tape
06/29/1999US5917234 Semiconductor device
06/29/1999US5917231 Semiconductor device including an insulative layer having a gap
06/29/1999US5917229 Programmable/reprogrammable printed circuit board using fuse and/or antifuse as interconnect
06/29/1999US5917228 Trench-type schottky-barrier diode
06/29/1999US5917225 Insulated gate field effect transistor having specific dielectric structures
06/29/1999US5917224 Compact ROM matrix
06/29/1999US5917223 Semiconductor device having salicide layer
06/29/1999US5917222 Intergrated circuit combining high frequency bipolar and high power CMOS transistors
06/29/1999US5917221 Semiconductor device and method for forming the same
06/29/1999US5917220 Integrated circuit with improved overvoltage protection
06/29/1999US5917219 Semiconductor devices with pocket implant and counter doping
06/29/1999US5917218 Peripheral circuits including high voltage transistors with LDD structures for nonvolatile memories
06/29/1999US5917217 Lateral field effect transistor and method of manufacturing the same
06/29/1999US5917215 Stepped edge structure of an EEPROM tunneling window
06/29/1999US5917214 Split gate flash memory unit
06/29/1999US5917213 Depletion compensated polysilicon electrodes
06/29/1999US5917212 Memory cell with capacitance for single event upset protection
06/29/1999US5917211 Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same
1 ... 5668 5669 5670 5671 5672 5673 5674 5675 5676 5677 5678 5679 5680 5681 5682 5683 5684 5685 5686 5687 5688 ... 6590