Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
11/1999
11/09/1999US5981385 Dimple elimination in a tungsten etch back process by reverse image patterning
11/09/1999US5981384 Method of intermetal dielectric planarization by metal features layout modification
11/09/1999US5981383 Method of fabricating a salicide layer of a device electrode
11/09/1999US5981382 Providing a dielectric layer having a opening with sidewall and a bottom, forming liner and nucleation layers, low power physical vapor deposition of aluminum, high power, physical vapor deposition of aluminum, annealing
11/09/1999US5981381 Method of manufacturing a semiconductor memory device
11/09/1999US5981380 Method of forming a local interconnect including selectively etched conductive layers and recess formation
11/09/1999US5981379 An inter-metal dielectric layer is formed by high density plasma chemical vapor deposition, an etch stop and oxide layers are formed, during etching an opening for via is formed and remaining etch stop work as protective layer
11/09/1999US5981378 Reliable interconnect via structures and methods for making the same
11/09/1999US5981377 Semiconductor device with improved trench interconnected to connection plug mating and method of making same
11/09/1999US5981376 Method of forming viahole
11/09/1999US5981375 Method of manufacturing a semiconductor device
11/09/1999US5981374 Sub-half-micron multi-level interconnection structure and process thereof
11/09/1999US5981373 Semiconductor device, method for manufacturing the same, apparatus for manufacturing the same
11/09/1999US5981372 Method for manufacturing a semiconductor device
11/09/1999US5981371 Bump forming method
11/09/1999US5981370 Method for maximizing interconnection integrity and reliability between integrated circuits and external connections
11/09/1999US5981369 Semiconductor integrated circuit device and process for manufacturing the same
11/09/1999US5981368 Enhanced shallow junction design by polysilicon line width reduction using oxidation with integrated spacer formation
11/09/1999US5981367 Method for making an access transistor
11/09/1999US5981366 Forming a tunnel oxide layer used for writing information on a silicon substrate, forming polysilicon layer on oxide, forming tungsten silicide layer over polysilicon using tungsten fluoride and silane dichloride gas, patterning
11/09/1999US5981365 Stacked poly-oxide-poly gate for improved silicide formation
11/09/1999US5981364 Method of forming a silicon gate to produce silicon devices with improved performance
11/09/1999US5981363 Method and apparatus for high performance transistor devices
11/09/1999US5981362 Manufacturing method of wiring
11/09/1999US5981361 Fabrication process of a semiconductor device including a dicing process of a semiconductor wafer
11/09/1999US5981359 Method of manufacturing semiconductor device having isolation film on SOI substrate
11/09/1999US5981358 Encroachless LOCOS isolation
11/09/1999US5981357 Semiconductor trench isolation with improved planarization methodology
11/09/1999US5981356 Isolation trenches with protected corners
11/09/1999US5981355 Method of forming isolating region
11/09/1999US5981354 Semiconductor fabrication employing a flowable oxide to enhance planarization in a shallow trench isolation process
11/09/1999US5981353 Method of forming a shallow trench isolation region
11/09/1999US5981352 Providing a semiconductor wafer having trench in a surface layer, depositing a bulk layer of tungsten in the trench layer, depositing a protective layer of equaxed grain tungsten over bulk layer
11/09/1999US5981351 Method of forming capacitor of a semiconductor device and a semiconductor capacitor formed thereby
11/09/1999US5981350 Method for forming high capacitance memory cells
11/09/1999US5981349 Method of forming semiconducting planar junction termination with high breakdown voltage and low parasitic capacitance
11/09/1999US5981348 Method for the manufacture of the extrinsic base of an NPN transistor in a high-frequency bipolar technology
11/09/1999US5981347 Multiple thermal annealing method for a metal oxide semiconductor field effect transistor with enhanced hot carrier effect (HCE) resistance
11/09/1999US5981346 Process for forming physical gate length dependent implanted regions using dual polysilicon spacers
11/09/1999US5981345 Si/SiGe MOSFET and method for fabricating the same
11/09/1999US5981344 Trench field effect transistor with reduced punch-through susceptibility and low RDSon
11/09/1999US5981343 Single feature size mos technology power device
11/09/1999US5981342 Method of making a semiconductor component with compensation implantation
11/09/1999US5981341 Sidewall spacer for protecting tunnel oxide during isolation trench formation in self-aligned flash memory core
11/09/1999US5981339 Narrower erase distribution for flash memory by smaller poly grain size
11/09/1999US5981338 High density flash memory
11/09/1999US5981337 Method of fabricating stack capacitor
11/09/1999US5981336 Process for forming double-layer crown capacitor
11/09/1999US5981334 Method of fabricating DRAM capacitor
11/09/1999US5981333 Methods of forming capacitors and DRAM arrays
11/09/1999US5981332 Increasing the gate threshold voltage, a thinner collar can be employed in the capacitor while achieving a desired level of leakage.
11/09/1999US5981331 Method of manufacturing a semiconductor memory device with a high dielectric constant capacitor
11/09/1999US5981330 Forming tungsten silicide to cover the polysilicon film, with a titanium layer covering tungsten silicide film, exposing polysilicon layer due to insufficinet coverage by silicide, covering titanium by titanium nitride, then titanium silicide
11/09/1999US5981329 SRAM cell employing substantially vertically elongated pull-up resistors and methods of making, and resistor constructions and methods of making
11/09/1999US5981328 Method of forming a high load resistance type static random access memory cell
11/09/1999US5981327 Method for forming wells of semiconductor device
11/09/1999US5981326 Damascene isolation of CMOS transistors
11/09/1999US5981325 Method for manufacturing CMOS
11/09/1999US5981324 Methods of forming integrated circuits having memory cell arrays and peripheral circuits therein
11/09/1999US5981321 Forming diffusion source layer on n-well and p-well region, field oxide layer and gates, forming photoresist over n-well and p-well region, doping p-type ions to a part of diffusion layer over n-well, removing photoresist over p-well region
11/09/1999US5981320 Method of fabricating cmosfet
11/09/1999US5981319 The feature in the second level is made to be larger than the first formed feature, thereby producing a structure that is larger at the top than at the base, i. e. t-shaped structure
11/09/1999US5981318 Fully-dielectric-isolated FET technology
11/09/1999US5981317 Method of fabricating a thin film transistor
11/09/1999US5981315 Transfer molding
11/09/1999US5981314 Near chip size integrated circuit package
11/09/1999US5981313 Structure and method for packaging a semiconductor device
11/09/1999US5981312 Curing encapsulant to form a bond between the substrate and integrated circuit chip
11/09/1999US5981311 Process for using a removeable plating bus layer for high density substrates
11/09/1999US5981309 Method for fabricating charge coupled device image sensor
11/09/1999US5981308 Method for manufacturing minute silicon mechanical device
11/09/1999US5981307 Fabrication process of optical semiconductor device having a diffraction grating
11/09/1999US5981303 Method of making field emitters with porous silicon
11/09/1999US5981302 Integrated multi-layer test pads and methods therefor
11/09/1999US5981301 Regeneration method and apparatus of wafer and substrate
11/09/1999US5981295 Ampule with integral filter
11/09/1999US5981150 Forming a substrate including, on the surface, first and second domains having different reflectivity to first light, covering the domains with positive resist, radiating to form pattern on the parts of domain with first light, developing
11/09/1999US5981149 Exposing resist film by radiation coated on a substrate to be etched via a photomask on which atleast a first and a second opening pattern are formed, developing to obtain pattern, etching the substrate to obtain predermined pattern
11/09/1999US5981148 Method for forming sidewall spacers using frequency doubling hybrid resist and device formed thereby
11/09/1999US5981146 Resist coating film
11/09/1999US5981145 Light absorbing polymers
11/09/1999US5981143 Chemically treated photoresist for withstanding ion bombarded processing
11/09/1999US5981142 Photoresist copolymer
11/09/1999US5981140 Positive photosensitive composition
11/09/1999US5981139 Photosensitive composition containing an aliphaticamine
11/09/1999US5981119 Exposing the resist to first monochromatic light of first frequency, a respective first machine focus is determined for first light, interrogating each latent image, determining maximum scattered energy, then averaging
11/09/1999US5981117 Scanning exposure method utilizing identical scan direction across multiple mask pattern layers
11/09/1999US5981116 A pattern of mask is transferred onto a photosensitive substrate by scanning the mask and photosensitive substrate in a synchronous manner
11/09/1999US5981114 Photoresist check patterns in highly integrated circuits having multi-level interconnect layers
11/09/1999US5981109 Forming an attenuating phase shifting material using a composite of a first material with a high extinction coefficient and a second material with a high index of refraction to achieve desired optical properties
11/09/1999US5981085 Composite substrate for heat-generating semiconductor device and semiconductor apparatus using the same
11/09/1999US5981075 For optical lenses, mirrors; durability
11/09/1999US5981001 Processing method for selectively irradiating a surface in presence of a reactive gas to cause etching
11/09/1999US5981000 Method for fabricating a thermally stable diamond-like carbon film
11/09/1999US5980999 Method of manufacturing thin film and method for performing precise working by radical control and apparatus for carrying out such methods
11/09/1999US5980979 A two-step adhesion layer deposition process with an intermediate particle removing step is to ensure sidewalls and bottom surfaces of vias are adequately covered with adhesion layer material prior to via plug formation
11/09/1999US5980978 Reacting a grignard reagent with a metal halide in an amine solvent
11/09/1999US5980775 Composition and slurry useful for metal CMP
11/09/1999US5980770 Removal of post-RIE polymer on Al/Cu metal line
11/09/1999US5980769 Plasma etching method
1 ... 5615 5616 5617 5618 5619 5620 5621 5622 5623 5624 5625 5626 5627 5628 5629 5630 5631 5632 5633 5634 5635 ... 6590