Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
11/1999
11/23/1999US5990515 Trenched gate non-volatile semiconductor device and method with corner doping and sidewall doping
11/23/1999US5990514 Nonvolatile semiconductor memory having boosting lines self-aligned with word lines
11/23/1999US5990513 Yield enhancement technique for integrated circuit processing to reduce effects of undesired dielectric moisture retention and subsequent hydrogen out-diffusion
11/23/1999US5990511 Memory cell with transfer device node in selective polysilicon
11/23/1999US5990510 Dynamic random access memory device and method for fabricating the same
11/23/1999US5990509 2F-square memory cell for gigabit memory applications
11/23/1999US5990508 Ferroelectric memory
11/23/1999US5990507 Multilayer; transistor, dielectric, capacitors
11/23/1999US5990502 High density gate array cell architecture with metallization routing tracks having a variable pitch
11/23/1999US5990501 Multichip press-contact type semiconductor device
11/23/1999US5990493 Diamond etch stop rendered conductive by a gas cluster ion beam implant of titanium
11/23/1999US5990492 Self-aligned thin-film transistor for a liquid crystal display having source and drain electrodes of different material
11/23/1999US5990491 Active matrix device utilizing light shielding means for thin film transistors
11/23/1999US5990489 Thin film semiconductor apparatus and production method thereof
11/23/1999US5990477 Apparatus for machining, recording, and reproducing, using scanning probe microscope
11/23/1999US5990453 High pressure/high temperature process chamber
11/23/1999US5990338 Negative-working chemical-sensitization photoresist composition
11/23/1999US5990060 Cleaning liquid and cleaning method
11/23/1999US5990022 Method of evaluating a silicon wafer
11/23/1999US5990021 Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture
11/23/1999US5990020 Method for forming a conductive plug
11/23/1999US5990019 Selective etching of oxides
11/23/1999US5990018 Forming an oxide layer on a conductive layer, patterning a photoresist layer on oxide layer, removing the oxide layer uncovered by said photoresist by reactive ion etching, and immersing oxide layer in nitrogen plasma; prevents bubbles
11/23/1999US5990017 Plasma reactor with heated source of a polymer-hardening precursor material
11/23/1999US5990016 Dry etching method and apparatus for manufacturing a semiconductor device
11/23/1999US5990015 Dual damascence process
11/23/1999US5990014 Combustion product formed in a combustion reactor from the spontaneous combustion of halogenated hydrocarbon and oxygen is contacted with wafers in low pressure furnace to remove group 1a and 2a metals; then combustion product purged
11/23/1999US5990013 Process for treating a semiconductor substrate comprising a surface-treatment step
11/23/1999US5990011 Titanium aluminum alloy wetting layer for improved aluminum filling of damescene trenches
11/23/1999US5990010 Pre-conditioning polishing pads for chemical-mechanical polishing
11/23/1999US5990009 Maximization of low dielectric constant material between interconnect traces of a semiconductor circuit
11/23/1999US5990008 Semiconductor device with pure copper wirings and method of manufacturing a semiconductor device with pure copper wirings
11/23/1999US5990007 Method of manufacturing a semiconductor device
11/23/1999US5990006 Method for forming materials
11/23/1999US5990005 Method of burying a contact hole with a metal for forming multilevel interconnections
11/23/1999US5990004 Method for forming a tungsten plug and a barrier layer in a contact of high aspect ratio
11/23/1999US5990003 Method of fabricating a semiconductor device
11/23/1999US5990002 Method of making an antireflective structure
11/23/1999US5990001 Method of forming a semiconductor device having a critical path wiring
11/23/1999US5990000 Method and apparatus for improving gap-fill capability using chemical and physical etchbacks
11/23/1999US5989999 Construction of a tantalum nitride film on a semiconductor wafer
11/23/1999US5989998 For semiconductor devices; by plasma polymerization or oxidizing an alkoxy(alkyl or phenyl)silane compound of given formula to yield a silicon oxide film containing an organic component not regularly arranged
11/23/1999US5989997 Method for forming dual damascene structure
11/23/1999US5989996 Method for manufacturing semiconductor device
11/23/1999US5989995 Semiconductor device and wire bonding method therefor
11/23/1999US5989993 Preparing bump structure(s) on a substrate for bonding; metallic underbump electroless metallization of two subsequent layers, the first deposition being thicker than the second; cost efficiency
11/23/1999US5989992 Method of making a semiconductor device
11/23/1999US5989989 Die and cube reroute process
11/23/1999US5989988 Semiconductor device and method of manufacturing the same
11/23/1999US5989987 Method of forming a self-aligned contact in semiconductor fabrications
11/23/1999US5989986 Method to inhibit the formation of ion implantation induced edge defects
11/23/1999US5989985 Semiconductor single crystalline substrate and method for production thereof
11/23/1999US5989984 Method of using getter layer to improve metal to metal contact resistance at low radio frequency power
11/23/1999US5989983 Method of fabricating and curing spin-on-glass layers by electron beam irradiation
11/23/1999US5989982 Semiconductor device and method of manufacturing the same
11/23/1999US5989981 Method of manufacturing SOI substrate
11/23/1999US5989980 Semiconductor processing method of forming field isolation oxide relative to a semiconductor substrate
11/23/1999US5989979 Silicon nitride(si3n4) foot is minimized by anisotropic plasma etching, which forms a polymer on the sidewalls of the photoresist layer, prevents lateral etching of photoresist and minimizes the critical dimension bias during si3n4 etch
11/23/1999US5989978 Shallow trench isolation of MOSFETS with reduced corner parasitic currents
11/23/1999US5989977 Shallow trench isolation process
11/23/1999US5989975 Method for manufacturing shallow trench isolation
11/23/1999US5989974 Method of manufacturing a semiconductor device
11/23/1999US5989973 Semiconductor processing method of providing a conductively doped layer of hemispherical grain polysilicon and a hemispherical grain polysilicon layer produced according to the method
11/23/1999US5989972 Capacitor in a semiconductor configuration and process for its production
11/23/1999US5989971 Method for forming trenched polysilicon structure
11/23/1999US5989970 Method for fabricating semiconductor device having thin-film resistor
11/23/1999US5989969 Method of producing silicon layer having surface controlled to be uneven
11/23/1999US5989968 Method of making bipolar transistor having reduced resistance
11/23/1999US5989967 Transistor with ultra short length defined partially by sidewall oxidation of a gate conductor overlying the channel length
11/23/1999US5989966 Method and a deep sub-micron field effect transistor structure for suppressing short channel effects
11/23/1999US5989965 Nitride overhang structures for the silicidation of transistor electrodes with shallow junction
11/23/1999US5989964 Post-spacer LDD implant for shallow LDD transistor
11/23/1999US5989963 Doping beneath the surface of substrate; forming retrograde channel profile by annealing in an inert gas to prevent an oxide capping layer from forming on surface; doping; heating in inert gas under vacuum; conventional dopants
11/23/1999US5989962 Semiconductor device having dual gate and method of formation
11/23/1999US5989961 Fabrication method of a vertical channel transistor
11/23/1999US5989960 Semiconductor device and method for fabricating the same
11/23/1999US5989959 Silicon nitride and silicon oxide films are deposited in that order on a metal silicide film; in a single session of lithography, the gate electrode of a transistor constituting a peripheral circuit are formed; use in flash memory
11/23/1999US5989957 Process for fabricating semiconductor memory device with high data retention including silicon oxynitride etch stop layer formed at high temperature with low hydrogen ion concentration
11/23/1999US5989956 DRAM capacitor process
11/23/1999US5989955 Method of forming stacked and trench type DRAM capacitor
11/23/1999US5989954 Method for forming a cylinder capacitor in the dram process
11/23/1999US5989953 Method for manufacturing DRAM capacitor
11/23/1999US5989952 Method for fabricating a crown-type capacitor of a DRAM cell
11/23/1999US5989951 Semiconductor device with contacts formed in self-alignment
11/23/1999US5989950 Reduced mask CMOS salicided process
11/23/1999US5989949 Method of manufacturing a complementary metal-oxide semiconductor device
11/23/1999US5989948 Defining low and high voltage tolerant regions on first and second substrate surfaces, respectively; improving lifetime of low voltage tolerant transistor by cleaning first substrate with hydrofluoric acid and hydrochloric acid
11/23/1999US5989947 Method for the manufacture of quantum structures, in particular quantum dots and tunnel barriers as well as components with such quantum structures
11/23/1999US5989946 Method of forming SRAM cells and pairs of field effect transistors
11/23/1999US5989945 One thin film in the thin film monolithic structure is formed of a coating film (excluding a spin-on-glass comprising siloxane bonds) such as polysilazanes, obtained by applying the solution and annealing; cost efficiency
11/23/1999US5989944 Method of fabricating self-aligned thin film transistor using laser irradiation
11/23/1999US5989943 Method for fabrication of programmable interconnect structure
11/23/1999US5989940 Cramping outer leads between mold halves which form a first cavity; injecting a first mold resin into cavity to seal semiconductor element; sealing first mold resin portion by a second mold resin to expose first part of mold portion
11/23/1999US5989939 Process of manufacturing compliant wirebond packages
11/23/1999US5989938 Thin oxynitride layer which defines a recess in a patterned metal layer, spin-on-glass(sog) fills recess and surface of oxynitride layer, removing sog from surface; adding second oxynitride layer and nitride layer; crack resistance
11/23/1999US5989937 Method for compensating for bottom warpage of a BGA integrated circuit
11/23/1999US5989936 Microelectronic assembly fabrication with terminal formation from a conductive layer
11/23/1999US5989935 Column grid array for semiconductor packaging and method
11/23/1999US5989934 Process for manufacturing a semiconductor device having a logic circuit and a plurality of input/output amplifier circuits
11/23/1999US5989929 Reactor for etching, fluorocarbon gas supply means, plasma generator, adjustable means for changing the oxygen concentration disposed to have a surface exposed; preventing etch stop layer during formation of deep holes
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