Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
11/1999
11/16/1999US5986447 Test head structure for integrated circuit tester
11/16/1999US5986348 Magnetic alignment system for bumps on an integrated circuit device
11/16/1999US5986347 Processing methods of forming contact openings and integrated circuitry
11/16/1999US5986346 Semiconductor device with improved pad connection
11/16/1999US5986344 Anti-reflective coating layer for semiconductor device
11/16/1999US5986343 Bond pad design for integrated circuits
11/16/1999US5986341 Semiconductor device
11/16/1999US5986338 Assembly of semiconductor device
11/16/1999US5986335 Semiconductor device having a tapeless mounting
11/16/1999US5986330 Enhanced planarization technique for an integrated circuit
11/16/1999US5986329 Deposition of super thin PECVD SiO2 in multiple deposition station system
11/16/1999US5986328 Buried contact architecture
11/16/1999US5986326 Semiconductor device with microwave bipolar transistor
11/16/1999US5986325 Microwave integrated circuit device
11/16/1999US5986323 High-frequency bipolar transistor structure
11/16/1999US5986322 Reduced leakage antifuse structure
11/16/1999US5986321 Double density fuse bank for the laser break-link programming of an integrated circuit
11/16/1999US5986320 Semiconductor integrated circuit device
11/16/1999US5986318 (Ge,Si) Nx anti-reflective compositions and integrated circuit devices comprising the same
11/16/1999US5986315 Guard wall to reduce delamination effects within a semiconductor die
11/16/1999US5986314 Depletion mode MOS capacitor with patterned Vt implants
11/16/1999US5986313 Semiconductor device comprising MISFETS and method of manufacturing the same
11/16/1999US5986312 Field effect semiconductor device having improved connections
11/16/1999US5986311 Semiconductor device having recrystallized source/drain regions
11/16/1999US5986310 Prolonging a polysilicon layer in smaller memory cells to prevent polysilicon load punch through
11/16/1999US5986308 MOS transistor with a protection diode
11/16/1999US5986306 Thin film transistor having a heat sink that exhibits a high degree of heat dissipation effect
11/16/1999US5986305 Semiconductor device with an inverse-T gate lightly-doped drain structure
11/16/1999US5986304 Punch-through prevention in trenched DMOS with poly-silicon layer covering trench corners
11/16/1999US5986303 Flash memory device and method for manufacturing the same
11/16/1999US5986302 Semiconductor memory device
11/16/1999US5986301 Thin film capacitor with electrodes having a perovskite structure and a metallic conductivity
11/16/1999US5986300 Semiconductor memory device and method of manufacturing the same
11/16/1999US5986299 Semiconductor integrated circuit device having multi-level wiring capacitor structures
11/16/1999US5986298 Matrix type multiple numeration system ferroelectric random access memory using leakage current
11/16/1999US5986295 Charge coupled device
11/16/1999US5986294 Semiconductor integrated circuit
11/16/1999US5986287 Semiconductor structure for a transistor
11/16/1999US5986286 Semiconductor device and a method of manufacturing the same
11/16/1999US5986284 Semiconductor device
11/16/1999US5986283 Test structure for determining how lithographic patterning of a gate conductor affects transistor properties
11/16/1999US5986282 Method of measuring electrical characteristics of semiconductor circuit in wafer state and semiconductor device for the same
11/16/1999US5986281 Circuit and method for predicting failure rates in a semiconductor device
11/16/1999US5986263 Electron beam inspection method and apparatus and semiconductor manufacturing method and its manufacturing line utilizing the same
11/16/1999US5986235 Method of efficiently laser marking singulated semiconductor devices
11/16/1999US5986218 Circuit board with conductor layer for increased breakdown voltage
11/16/1999US5986209 Package stack via bottom leaded plastic (BLP) packaging
11/16/1999US5986045 Reaction of haloarylene compound with diphenol compound to form polyarylene ether
11/16/1999US5985972 Acrylic sheet having uniform distribution of coloring and mineral filler before and after thermoforming
11/16/1999US5985811 Cleaning solution and cleaning method
11/16/1999US5985771 Semiconductor wafer assemblies comprising silicon nitride, methods of forming silicon nitride, and methods of reducing stress on semiconductive wafers
11/16/1999US5985770 Method of depositing silicon oxides
11/16/1999US5985769 Semiconductor substrate is prepared which has an interconnection pattern formed thereon
11/16/1999US5985768 Method of forming a semiconductor
11/16/1999US5985767 Facet etch for improved step coverage of integrated circuit contacts
11/16/1999US5985766 Semiconductor processing methods of forming a contact opening
11/16/1999US5985765 Method for reducing bonding pad loss using a capping layer when etching bonding pad passivation openings
11/16/1999US5985763 Construction of metal-to-metal connections between non-adjacent layers in structure, such as semiconductor device
11/16/1999US5985762 Preventing copper poisoning while fabricating an integrated circuit structure
11/16/1999US5985761 Method of making an integrated circuit structure with planarized layer
11/16/1999US5985760 Method for manufacturing a high density electronic circuit assembly
11/16/1999US5985759 Oxygen enhancement of ion metal plasma (IMP) sputter deposited barrier layers
11/16/1999US5985758 Depositing copper or aluminum film over an antidiffusionmetal layer on structure formed with a metal contact, annealing to planarize it
11/16/1999US5985757 Heating wafer with silicon oxide film under high vacuumpresputtering under inert gas, sputtering using platinum target, stabilizing by annealing, cooling
11/16/1999US5985756 Method of forming an interconnection in a contact hole in an insulation layer over a silicon substrate
11/16/1999US5985754 Method of forming a void-free contact plug
11/16/1999US5985753 Method to manufacture dual damascene using a phantom implant mask
11/16/1999US5985752 Self-aligned via structure and method of manufacture
11/16/1999US5985751 Process for fabricating interconnection of semiconductor device
11/16/1999US5985750 Selectively etching aluminum wires, reforming surface of oxide film beneath wires, forming an organic ingterlayer film
11/16/1999US5985749 Method of forming a via hole structure including CVD tungsten silicide barrier layer
11/16/1999US5985748 Method of making a semiconductor device using chemical-mechanical polishing having a combination-step process
11/16/1999US5985747 High pressure reflow for plugging wiring material into contact holes and grooves of inner layer insulation
11/16/1999US5985746 Process for forming self-aligned conductive plugs in multiple insulation levels in integrated circuit structures and resulting product
11/16/1999US5985745 Method of forming a via hole filled with a conducting material, and separater from a gate structure by an insulating material
11/16/1999US5985744 Forming a silicide in predetermined areas of a semiconductor device
11/16/1999US5985743 Single mask substrate doping process for CMOS integrated circuits
11/16/1999US5985742 Controlled cleavage process and device for patterned films
11/16/1999US5985741 Controlling crystallization by using a metal containing crystallization promoter to at least one portion of semiconductor layer
11/16/1999US5985740 Crystallizing amorphous semiconductor film by first heat treatment and reducing catalyst existing in film by a second heat treatment within an oxidizing atmosphere containing a halogen
11/16/1999US5985739 Semiconductor structures having advantageous high-frequency characteristics and processes for producing such semiconductor structures
11/16/1999US5985738 Method for forming field oxide of semiconductor device using wet and dry oxidation
11/16/1999US5985737 Forming first a pad oxide layer, then silicon nitride layer,patternikng to etch the two layers, exposing portion ofsubstrate
11/16/1999US5985736 Process for forming field isolation
11/16/1999US5985735 Etching trench in semiconductor substrate, forming firstoxide layer, surface treatment with nitrogen plasma, depositing second oxie layer by chemical vapor deposition process using gases other than ozone
11/16/1999US5985734 Method for fabricating a semiconductor device
11/16/1999US5985733 Semiconductor device having a T-shaped field oxide layer and a method for fabricating the same
11/16/1999US5985732 Method of forming integrated stacked capacitors with rounded corners
11/16/1999US5985731 Method for forming a semiconductor device having a capacitor structure
11/16/1999US5985730 Forming charge storage electrode on substrate, nitrifying surface, plasma treating and oxidizing, depositing tantalum oxide film, heating, forming plate electrode
11/16/1999US5985729 Method for manufacturing a capacitor of a trench DRAM cell
11/16/1999US5985728 Silicon on insulator process with recovery of a device layer from an etch stop layer
11/16/1999US5985727 Method for forming MOS devices with retrograde pocket regions and counter dopant regions buried in the substrate surface
11/16/1999US5985726 Damascene process for forming ultra-shallow source/drain extensions and pocket in ULSI MOSFET
11/16/1999US5985725 Method for manufacturing dual gate oxide layer
11/16/1999US5985724 Method for forming asymmetrical p-channel transistor having nitrided oxide patterned to selectively form a sidewall spacer
11/16/1999US5985723 ROM coding by neuron activation
11/16/1999US5985722 Method of fabricating electrostatic discharge device
11/16/1999US5985721 Single feature size MOS technology power device
11/16/1999US5985720 Method of making non-volatile semiconductor memory device with the floating gate having upper and lower impurity concentrations
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