Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
05/2000
05/09/2000US6060744 Semiconductor device with a main current cell region and a current detecting cell region
05/09/2000US6060740 Non-volatile semiconductor memory device and method for manufacturing the same
05/09/2000US6060739 Non-volatile semiconductor memory device having a floating gate inside a grove
05/09/2000US6060738 Semiconductor device having SOI structure
05/09/2000US6060736 Semiconductor device and method of manufacturing the same
05/09/2000US6060735 Thin film dielectric device
05/09/2000US6060734 MESfield effect transistor
05/09/2000US6060733 Formation of lightly doped regions under a gate having a reduced gate oxide
05/09/2000US6060732 Solid state image sensor and method for fabricating the same
05/09/2000US6060730 Semiconductor light emitting device
05/09/2000US6060729 Light-emitting device
05/09/2000US6060726 CMOS transistor with two channel regions and common gate
05/09/2000US6060725 Thin film transistor using a semiconductor film
05/09/2000US6060723 Controllable conduction device
05/09/2000US6060721 Apparatus for detecting correct positioning of a wafer cassette
05/09/2000US6060718 Ion source having wide output current operating range
05/09/2000US6060717 Charged particle beam exposure method and charged particle beam exposure apparatus therefor
05/09/2000US6060716 Electron beam lithography method
05/09/2000US6060697 Substrate processing apparatus having regulated power consumption and method therefor
05/09/2000US6060664 Electronic circuit component
05/09/2000US6060406 MOS transistors with improved gate dielectrics
05/09/2000US6060405 Method of deposition on wafer
05/09/2000US6060404 In-situ deposition of stop layer and dielectric layer during formation of local interconnects
05/09/2000US6060403 Method of manufacturing semiconductor device
05/09/2000US6060402 Process for selective recess etching of epitaxial field effect transistors with a novel etch-stop layer
05/09/2000US6060401 Method of fabricating dual cylindrical capacitor
05/09/2000US6060400 Highly selective chemical dry etching of silicon nitride over silicon and silicon dioxide
05/09/2000US6060399 Method for isolating semiconductor devices
05/09/2000US6060398 Guard cell for etching
05/09/2000US6060397 Flowing nitrogen, oxygen and perfluoroethane
05/09/2000US6060396 Polishing agent used for polishing semiconductor silicon wafers and polishing method using the same
05/09/2000US6060395 Planarization method using a slurry including a dispersant
05/09/2000US6060394 Method for forming shallow trench isolation with global planarization
05/09/2000US6060393 Deposition control of stop layer and dielectric layer for use in the formation of local interconnects
05/09/2000US6060392 Pulsing ultraviolet radiation to amorphous silicon to react with refractory metal to form heat resistante silicide
05/09/2000US6060391 Monitoring partial pressure of organic metal raw material gas depending on emission intensity of light
05/09/2000US6060390 Method of forming wiring layer
05/09/2000US6060389 Nitriding barrier layer from tetrakis/dimethylamino/titanium entrained gas
05/09/2000US6060388 Conductors for microelectronic circuits and method of manufacture
05/09/2000US6060387 Transistor fabrication process in which a contact metallization is formed with different silicide thickness over gate interconnect material and transistor source/drain regions
05/09/2000US6060386 Method and apparatus for forming features in holes, trenches and other voids in the manufacturing of microelectronic devices
05/09/2000US6060385 Method of making an interconnect structure
05/09/2000US6060384 Depositing a dielectric layer of hydrogen silsesquioxane (hsq) containing si--h bonds, forming an opening in above layer to expose conductive layer, treating dielectric layer hydrogen plasma, filling the gap with conductive material
05/09/2000US6060383 Method for making multilayered coaxial interconnect structure
05/09/2000US6060382 Method for forming insulating film between metal wirings of semiconductor device
05/09/2000US6060381 Method of manufacturing an electronic part having an air-bridge interconnection
05/09/2000US6060380 Etching an opening in an integrated circuit by depositing a siliconoxynitride hardmask layer over first insulating layer which is antirefective to light that is used for exposing photoresist layer
05/09/2000US6060379 Method of forming dual damascene structure
05/09/2000US6060377 Thermal silicidation of polycrystalline silicon layer and metal layer
05/09/2000US6060376 Integrated etch process for polysilicon/metal gate
05/09/2000US6060375 Process for forming re-entrant geometry for gate electrode of integrated circuit structure
05/09/2000US6060374 Monitor for molecular nitrogen during silicon implant
05/09/2000US6060373 Method for manufacturing a flip chip semiconductor device
05/09/2000US6060372 Method for making a semiconductor device with improved sidewall junction capacitance
05/09/2000US6060371 Process for forming a trench device isolation region on a semiconductor substrate
05/09/2000US6060370 Method for shallow trench isolations with chemical-mechanical polishing
05/09/2000US6060369 Forming a first oxide layer containing a nitrogen on the substrate where a portion of nitrogen diffuses to substrate forming nitrogen doped region, nitrogen is doped through oxide layer increases nitrogen concentration in doped region
05/09/2000US6060368 Mask pattern correction method
05/09/2000US6060367 Method of forming capacitors
05/09/2000US6060366 Method for manufacturing dram capacitor incorporating liquid phase deposition
05/09/2000US6060365 Method for fabricating a bipolar transistor
05/09/2000US6060364 Fast Mosfet with low-doped source/drain
05/09/2000US6060363 Method of manufacturing semiconductor device
05/09/2000US6060362 Methods of fabricating field effect transistors including side branch grooves
05/09/2000US6060361 The tungsten silicon nitride layer formed by the plasma treatment has an amorphous internal structure, and an additional paths for diffusion are created inside tungsten silicon nitride layer for dopes inside polysilcon layer
05/09/2000US6060360 Method of manufacture of P-channel EEprom and flash EEprom devices
05/09/2000US6060359 Flash memory cell and method of fabricated the same
05/09/2000US6060358 Damascene NVRAM cell and method of manufacture
05/09/2000US6060357 Method of manufacturing flash memory
05/09/2000US6060356 Method of fabricating virtual ground SSI flash EPROM cell and array
05/09/2000US6060355 Process for improving roughness of conductive layer
05/09/2000US6060354 Depositing polysilicon onto an insulating layer to form a base polysilicon layer, masking the polysilicon layer, depositing insitu polysilicon on masking layer through gas phase nucleation to form vertical wall, etching
05/09/2000US6060353 Method of forming a ring shaped storage node structure for a DRAM capacitor structure
05/09/2000US6060352 Method of manufacturing semiconductor device with increased focus margin
05/09/2000US6060351 Process for forming capacitor over bit line memory cell
05/09/2000US6060350 Semiconductor memory device having word line conductors provided at lower level than memory cell capacitor and method of manufacturing same
05/09/2000US6060349 Planarization on an embedded dynamic random access memory
05/09/2000US6060348 Method to fabricate isolation by combining locos and shallow trench isolation for ULSI technology
05/09/2000US6060347 Method for preventing damage to gate oxide from well in complementary metal-oxide semiconductor
05/09/2000US6060346 Semiconductor device and method for manufacturing the same
05/09/2000US6060345 Method of making NMOS and PMOS devices with reduced masking steps
05/09/2000US6060344 Method for producing a semiconductor substrate
05/09/2000US6060343 Applying a polycyanurate resin on a surface of the fabricated wafer to form a buffer layer and curing
05/09/2000US6060341 Method of making an electronic package
05/09/2000US6060340 Packing method of semiconductor device
05/09/2000US6060335 Semiconductor light emitting device and method of manufacturing the same
05/09/2000US6060330 Method of customizing integrated circuits by selective secondary deposition of interconnect material
05/09/2000US6060328 Methods and arrangements for determining an endpoint for an in-situ local interconnect etching process
05/09/2000US6060212 193 nm positive-working photoresist composition
05/09/2000US6060176 Corrosion protection for metallic features
05/09/2000US6060132 Forming silicon oxynitride and silicon nitride coatings without contaminating photoresist by holding wafer in vacuum to prevent explosion, adding gas mixture of silane, oxygen, nitrogen and subjecting to radio frequency electrical signal
05/09/2000US6060130 Method of forming insulation films for liquid crystal display
05/09/2000US6060127 Mechanically restricted laser deposition
05/09/2000US6060119 Compound tertiarybutylbis-(dimethylamino)phosphine and a process for preparing the compound tertiarybutylbis-(dimethylamino)phosphine
05/09/2000US6059986 Wet station apparatus having quartz heater monitoring system and method of monitoring thereof
05/09/2000US6059985 Method of processing a substrate and apparatus for the method
05/09/2000US6059984 Forming alumina layer; masking; etching
05/09/2000US6059981 Fiducial marks for charged-particle-beam exposure apparatus and methods for forming same
05/09/2000US6059952 Method of fabricating coated powder materials and their use for high conductivity paste applications
05/09/2000US6059945 Sputter target for eliminating redeposition on the target sidewall
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