Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
08/2013
08/20/2013US8513777 Method and apparatus for generating reticle data
08/20/2013US8513776 Semiconductor device and method capable of scribing chips with high yield
08/20/2013US8513771 Semiconductor package with integrated inductor
08/20/2013US8513769 Electrical fuses and resistors having sublithographic dimensions
08/20/2013US8513767 Package interconnects
08/20/2013US8513766 Semiconductor device having a drain-gate isolation portion
08/20/2013US8513765 Formation method and structure for a well-controlled metallic source/drain semiconductor device
08/20/2013US8513764 Schottky diode
08/20/2013US8513757 Cover for image sensor assembly with light absorbing layer and alignment features
08/20/2013US8513756 Semiconductor package and manufacturing method for a semiconductor package as well as optical module
08/20/2013US8513750 Forming inductor and transformer structures with magnetic materials using damascene processing for integrated circuits
08/20/2013US8513739 Metal-gate high-k reference structure
08/20/2013US8513733 Edge termination region of a semiconductor device
08/20/2013US8513732 High voltage power MOSFET having low on-resistance
08/20/2013US8513726 EEPROM with increased reading speed
08/20/2013US8513725 Nonvolatile semiconductor memory device and method of manufacturing the same
08/20/2013US8513720 Metal oxide semiconductor thin film transistors
08/20/2013US8513711 Gas-sensitive semiconductor device
08/20/2013US8513707 RF CMOS transistor design
08/20/2013US8513705 Power electronic devices, methods of manufacturing the same, and integrated circuit modules including the same
08/20/2013US8513704 Method for manufacturing a photodiode and corresponding photodiode and electromagnetic radiation detector
08/20/2013US8513703 Group III-nitride HEMT with multi-layered substrate having a second layer of one conductivity type touching a top surface of a first layers of different conductivity type and a method for forming the same
08/20/2013US8513702 Use of a metal complex as a p-dopant for an organic semiconductive matrix material, organic semiconductor material and organic light-emitting diodes
08/20/2013US8513694 Nitride semiconductor device and manufacturing method of the device
08/20/2013US8513678 Light-emitting device
08/20/2013US8513672 Wafer precursor prepared for group III nitride epitaxial growth on a composite substrate having diamond and silicon carbide layers, and semiconductor laser formed thereon
08/20/2013US8513670 Pixel structure and pixel circuit having multi-display mediums
08/20/2013US8513667 Thin film transistor array panel and manufacturing method thereof
08/20/2013US8513666 Semiconductor device and manufacturing method thereof
08/20/2013US8513660 Organic optoelectronic device and making method thereof
08/20/2013US8513653 Electronic device using a two-dimensional sheet material, transparent display and methods of fabricating the same
08/20/2013US8513652 Organic light emitting display apparatus and method of manufacturing the same
08/20/2013US8513640 Semiconductor device
08/20/2013US8513587 Image sensor with anti-reflection layer and method of manufacturing the same
08/20/2013US8513143 Semiconductor structure and method of manufacturing
08/20/2013US8513142 Method of manufacturing non-photosensitive polyimide passivation layer
08/20/2013US8513141 Defect etching of germanium
08/20/2013US8513140 Post-dry etching cleaning liquid composition and process for fabricating semiconductor device
08/20/2013US8513139 Etching agent, etching method and liquid for preparing etching agent
08/20/2013US8513138 Gas cluster ion beam etching process for Si-containing and Ge-containing materials
08/20/2013US8513137 Plasma processing apparatus and plasma processing method
08/20/2013US8513136 Memory devices and method of manufacturing the same
08/20/2013US8513135 Methods of modifying oxide spacers
08/20/2013US8513134 Semiconductor device producing method
08/20/2013US8513133 Composition for forming resist underlayer film and method for forming pattern
08/20/2013US8513132 Method for fabricating metal pattern in semiconductor device
08/20/2013US8513131 Fin field effect transistor with variable channel thickness for threshold voltage tuning
08/20/2013US8513130 Semiconductor substrate and method of fabricating semiconductor device
08/20/2013US8513129 Planarizing etch hardmask to increase pattern density and aspect ratio
08/20/2013US8513128 Poly opening polish process
08/20/2013US8513127 Chemical mechanical planarization processes for fabrication of FinFET devices
08/20/2013US8513126 Slurry composition having tunable dielectric polishing selectivity and method of polishing a substrate
08/20/2013US8513125 Manufacturing a microelectronic device comprising silicon and germanium nanowires integrated on a same substrate
08/20/2013US8513124 Copper electroplating process for uniform across wafer deposition and void free filling on semi-noble metal coated wafers
08/20/2013US8513123 Method of manufacturing solid electrolytic capacitor
08/20/2013US8513122 Method and structure for differential silicide and recessed or raised source/drain to improve field effect transistor
08/20/2013US8513121 Semiconductor memory device and manufacturing method thereof
08/20/2013US8513120 Gold-tin etch using combination of halogen plasma and wet etch
08/20/2013US8513119 Method of forming bump structure having tapered sidewalls for stacked dies
08/20/2013US8513118 Method for producing compound semiconductor light-emitting device
08/20/2013US8513117 Process to remove Ni and Pt residues for NiPtSi applications
08/20/2013US8513116 Atomic layer deposition of tungsten materials
08/20/2013US8513115 Method of forming an interconnect structure having an enlarged region
08/20/2013US8513114 Method for forming a dual damascene interconnect structure
08/20/2013US8513112 Barrier-metal-free copper damascene technology using enhanced reflow
08/20/2013US8513111 Forming semiconductor structures
08/20/2013US8513110 Processes and structures for beveled slope integrated circuits for interconnect fabrication
08/20/2013US8513108 Apparatus, system, and method for wireless connection in integrated circuit packages
08/20/2013US8513107 Replacement gate FinFET devices and methods for forming the same
08/20/2013US8513106 Pseudo butted junction structure for back plane connection
08/20/2013US8513105 Flexible integration of logic blocks with transistors of different threshold voltages
08/20/2013US8513104 Methods of forming a floating junction on a solar cell with a particle masking layer
08/20/2013US8513103 Method for manufacturing vertical transistor having buried junction
08/20/2013US8513102 Reduction of random telegraph signal (RTS) and 1/f noise in silicon MOS devices, circuits, and sensors
08/20/2013US8513101 Method of synthesizing nanowires
08/20/2013US8513100 Semiconductor device manufacturing method and semiconductor device
08/20/2013US8513099 Epitaxial source/drain contacts self-aligned to gates for deposited FET channels
08/20/2013US8513098 Semiconductor device and method of forming reconstituted wafer with larger carrier to achieve more eWLB packages per wafer with encapsulant deposited under temperature and pressure
08/20/2013US8513097 Plasma processing apparatus
08/20/2013US8513096 Wafer dividing method
08/20/2013US8513094 Method of manufacturing semiconductor device
08/20/2013US8513093 Substrate structure including functional region and method for transferring functional region
08/20/2013US8513092 Method for producing a stack of semi-conductor thin films
08/20/2013US8513091 Method for wafer bonding using gold and indium
08/20/2013US8513090 Method for manufacturing semiconductor substrate, and semiconductor device
08/20/2013US8513089 Discontinuous thin semiconductor wafer surface features
08/20/2013US8513088 Semiconductor device and method for manufacturing the same
08/20/2013US8513087 Processes for forming isolation structures for integrated circuit devices
08/20/2013US8513086 Methods for etching doped oxides in the manufacture of microfeature devices
08/20/2013US8513085 Structure and method to improve threshold voltage of MOSFETs including a high k dielectric
08/20/2013US8513084 Transistor structure with a sidewall-defined intrinsic base to extrinsic base link-up region and method of forming the transistor
08/20/2013US8513083 Methods of forming an anode and a cathode of a substrate diode by performing angled ion implantation processes
08/20/2013US8513082 Method for fabricating an electrostatic discharge protection device
08/20/2013US8513081 Carbon implant for workfunction adjustment in replacement gate transistor
08/20/2013US8513080 Reducing contamination in a process flow of forming a channel semiconductor alloy in a semiconductor device
08/20/2013US8513079 TFT SAS memory cell structures
08/20/2013US8513078 Structure and method for fabricating fin devices
08/20/2013US8513077 Semiconductor device and method of manufacturing the same
08/20/2013US8513076 Non-volatile memory device and method for fabricating the same
08/20/2013US8513075 Method for manufacturing a semiconductor device