Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
08/2013
08/15/2013US20130210231 Method of forming contact hole pattern
08/15/2013US20130210230 Method for providing electrical connections to spaced conductive lines
08/15/2013US20130210229 Silicon-containing surface modifier, resist lower layer film-forming composition containing the same, and patterning process
08/15/2013US20130210228 Method of forming pitch multiplied contacts
08/15/2013US20130210227 Use of contacts to create differential stresses on devices
08/15/2013US20130210226 Pattern formation method
08/15/2013US20130210225 Method for fabricating semiconductor device
08/15/2013US20130210224 Method and apparatus for dividing thin film device into separate cells
08/15/2013US20130210223 Methods of forming integrated circuit devices using modified rectangular mask patterns to increase reliability of contacts to electrically conductive lines
08/15/2013US20130210222 Semiconductor devices having conductive via structures and methods for fabricating the same
08/15/2013US20130210221 Selective epitaxial germanium growth on silicon-trench fill and in situ doping
08/15/2013US20130210220 Methods of forming reverse side engineered iii-nitride devices
08/15/2013US20130210218 Method for transferring a graphene layer
08/15/2013US20130210216 Epitaxial channel formation methods and structures
08/15/2013US20130210215 Packaging method with backside wafer dicing
08/15/2013US20130210214 Vertical integration of cmos electronics with photonic devices
08/15/2013US20130210213 Method for forming self-aligned overlay mark
08/15/2013US20130210212 Semiconductor Device Manufacturing Methods
08/15/2013US20130210209 Method of integrating a charge-trapping gate stack into a cmos flow
08/15/2013US20130210205 Manufacturing method of power transistor device with super junction
08/15/2013US20130210204 Method for etching polycrystalline silicon, method for manufacturing semiconductor device, and etching program
08/15/2013US20130210202 Method of planarizing substrate and method of manufacturing thin film transistor using the same
08/15/2013US20130210201 Method for manufacturing active array substrate
08/15/2013US20130210200 Method of manufacturing semiconductor device
08/15/2013US20130210198 Process for forming semiconductor structure
08/15/2013US20130210197 Leadframe based multi terminal ic package
08/15/2013US20130210195 Packaging method of molded wafer level chip scale package (wlcsp)
08/15/2013US20130210193 ReRAM STACKS PREPARATION BY USING SINGLE ALD OR PVD CHAMBER
08/15/2013US20130210188 Method and Apparatus for Reducing Stripe Patterns
08/15/2013US20130210182 Methods and apparatus for measuring analytes
08/15/2013US20130210174 Resin coating device and resin coating method
08/15/2013US20130210173 Multiple Zone Temperature Control for CMP
08/15/2013US20130210172 Wafer thinning apparatus having feedback control and method of using
08/15/2013US20130210171 Method for molecular adhesion bonding with compensation for radial misalignment
08/15/2013US20130210170 Apparatus And Method For Repairing An Integrated Circuit
08/15/2013US20130209991 Wireless swnt sensor integrated with microfluidic system for various liquid sensing applications
08/15/2013US20130209781 Dimensional silica-based porous silicon structures and methods of fabrication
08/15/2013US20130209211 Wafer inversion mechanism
08/15/2013US20130209205 System and method for offloading ic units
08/15/2013US20130209200 Carrier device
08/15/2013US20130209198 Techniques for handling media arrays
08/15/2013US20130207306 Methods for Molding Integrated Circuits
08/15/2013US20130207279 Method for manufacturing an integrated circuit comprising vias crossing the substrate
08/15/2013US20130207277 Electronic device and fabrication method thereof
08/15/2013US20130207276 Novel process for forming a big via
08/15/2013US20130207273 Metal Line and Via Formation Using Hard Masks
08/15/2013US20130207271 Semiconductor device, method for manufacturing semiconductor device, and electronic apparatus
08/15/2013US20130207270 Dual-metal self-aligned wires and vias
08/15/2013US20130207269 Semiconductor device and method of manufacturing the same
08/15/2013US20130207267 Interconnection structures in a semiconductor device and methods of manufacturing the same
08/15/2013US20130207265 Structure and method of making the same
08/15/2013US20130207264 Stress Reduction Apparatus
08/15/2013US20130207261 Maintaining alignment in a multi-chip module using a compressible structure
08/15/2013US20130207260 Semiconductor device and method for manufacturing the same
08/15/2013US20130207259 Method of manufacturing a semiconductor device and wafer
08/15/2013US20130207258 Post-passivation interconnect structure amd method of forming same
08/15/2013US20130207257 Semiconductor device and method for manufacturing the semiconductor device
08/15/2013US20130207256 Semiconductor device and manufacturing method thereof
08/15/2013US20130207255 Semiconductor device package having backside contact and method for manufacturing
08/15/2013US20130207254 Semiconductor chip, method for manufacturing a semiconductor chip, device and method for manufacturing a device
08/15/2013US20130207250 Chip attach frame
08/15/2013US20130207249 Assembly having stacked die mounted on substrate
08/15/2013US20130207247 Semiconductor Device and Method of Forming a Shielding Layer Over a Semiconductor Die After Forming a Build-up Interconnect Structure
08/15/2013US20130207245 Methods for making porous insulating films and semiconductor devices including the same
08/15/2013US20130207244 Process for fabricating a silicon-on-insulator structure
08/15/2013US20130207243 Method of Manufacturing a Semiconductor Device
08/15/2013US20130207237 Method for producing gallium nitride substrates for electronic and optoelectronic devices
08/15/2013US20130207235 Self-aligned emitter-base region
08/15/2013US20130207232 Semiconductor devices including capacitors and methods of manufacturing the same
08/15/2013US20130207230 On-chip ferrite bead inductor
08/15/2013US20130207228 Method of manufacturing semiconductor device and semiconductor device
08/15/2013US20130207227 Mosfet termination trench
08/15/2013US20130207226 Recessed device region in epitaxial insulating layer
08/15/2013US20130207225 Memory cell profiles
08/15/2013US20130207223 Semiconductor device and method for producing a semiconductor device
08/15/2013US20130207207 Method and apparatus for high pressure sensor device
08/15/2013US20130207205 Noise shielding techniques for ultra low current measurements in biochemical applications
08/15/2013US20130207204 Biosensor chip and a method of manufacturing the same
08/15/2013US20130207200 Integrated circuit having thinner gate dielectric and method of making
08/15/2013US20130207194 Transistors with uniaxial stress channels
08/15/2013US20130207191 Semiconductor structure and method for manufacturing the same
08/15/2013US20130207188 Junction butting on soi by raised epitaxial structure and method
08/15/2013US20130207187 Insulated gate bipolar transistor structure having low substrate leakage
08/15/2013US20130207185 Isolated device and manufacturing method thereof
08/15/2013US20130207183 Semiconductor device and method of fabricating the same
08/15/2013US20130207182 Semiconductor device and method of manufacturing the same
08/15/2013US20130207178 Semiconductor device and method of manufacturing the same
08/15/2013US20130207177 Nonvolatile memory device and method of manufacturing the same
08/15/2013US20130207176 Semiconductor device and method for manufacturing the same
08/15/2013US20130207175 Nonvolatile semiconductor storage device and method of manufacturing the same
08/15/2013US20130207174 Split-gate device and method of fabricating the same
08/15/2013US20130207173 Flash memory and method for fabricating the same
08/15/2013US20130207172 Trench mosfet having a top side drain
08/15/2013US20130207171 Semiconductor device having capacitor including high-k dielectric
08/15/2013US20130207170 Programmable logic device and method for manufacturing semiconductor device
08/15/2013US20130207166 Methods and Apparatus for Doped SiGe Source/Drain Stressor Deposition
08/15/2013US20130207163 Semiconductor Devices and Manufacturing Methods Thereof
08/15/2013US20130207162 High performance multi-finger strained silicon germanium channel pfet and method of fabrication
08/15/2013US20130207161 Semiconductor device and method for forming the same
08/15/2013US20130207122 Method for fabricating finfets and semiconductor structure fabricated using the method
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