| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 05/07/2002 | US6383945 High selectivity pad etch for thick topside stacks |
| 05/07/2002 | US6383944 Micropatterning method |
| 05/07/2002 | US6383943 Process for improving copper fill integrity |
| 05/07/2002 | US6383942 Dry etching method |
| 05/07/2002 | US6383941 Method of etching organic ARCs in patterns having variable spacings |
| 05/07/2002 | US6383940 Exposure method and apparatus |
| 05/07/2002 | US6383939 Method for etching memory gate stack using thin resist layer |
| 05/07/2002 | US6383938 Method of anisotropic etching of substrates |
| 05/07/2002 | US6383937 Method of fabricating a silicon island |
| 05/07/2002 | US6383936 Method for removing black silicon in semiconductor fabrication |
| 05/07/2002 | US6383935 Method of reducing dishing and erosion using a sacrificial layer |
| 05/07/2002 | US6383933 Method of using organic material to enhance STI planarization or other planarization processes |
| 05/07/2002 | US6383931 Etch uniformity |
| 05/07/2002 | US6383930 Method to eliminate copper CMP residue of an alignment mark for damascene processes |
| 05/07/2002 | US6383929 Forming interconnects over silk? polymer interlayer by depositing titanium, titanium nitride, and tantalum or tantalum nitride; nonalloying with copper; eliminates open circuits after heat treatment |
| 05/07/2002 | US6383928 Post copper CMP clean |
| 05/07/2002 | US6383927 Process for fabricating semiconductor device, apparatus using more than one kind of inert gas for evacuating air and method for entering wafer into the apparatus |
| 05/07/2002 | US6383926 Method of manufacturing a transistor |
| 05/07/2002 | US6383925 Treating copper or copper alloy interconnects with nitrogen and ammonia, depositing a silane, reducing the silane to silicon nitride with high density plasma; improved adhesion of nitride layer to copper |
| 05/07/2002 | US6383924 Method of forming buried conductor patterns by surface transformation of empty spaces in solid state materials |
| 05/07/2002 | US6383923 Article comprising vertically nano-interconnected circuit devices and method for making the same |
| 05/07/2002 | US6383922 Depositing cobalt on silicon, annealing and siliciding, depositing titanium and annealing again to form thermally stable cobalt disilicide; used in fabrication of integrated circuits |
| 05/07/2002 | US6383921 Self aligned silicide contact method of fabrication |
| 05/07/2002 | US6383920 Process of enclosing via for improved reliability in dual damascene interconnects |
| 05/07/2002 | US6383919 Method of making a dual damascene structure without middle stop layer |
| 05/07/2002 | US6383918 Method for reducing semiconductor contact resistance |
| 05/07/2002 | US6383917 Method for making integrated circuits |
| 05/07/2002 | US6383916 Top layers of metal for high performance IC's |
| 05/07/2002 | US6383915 Depositing titanium and titanium nitride using high density plasma, then depositing aluminum over the surface with a <111> rockwell curve fwhm angle of one degree or less; reduced pitting |
| 05/07/2002 | US6383914 Method of manufacturing an aluminum interconnect structure of a semiconductor device having <111> orientation |
| 05/07/2002 | US6383913 Method for improving surface wettability of low k material |
| 05/07/2002 | US6383912 Fabrication method of integrated circuits with multiple low dielectric-constant intermetal dielectrics |
| 05/07/2002 | US6383911 Trench interconnect formed in polyimide film using chemical vapor deposition and sputtering techniques; increased interlayer connection resistance |
| 05/07/2002 | US6383910 Method of manufacturing a semiconductor device, and a semiconductor device manufactured thereby |
| 05/07/2002 | US6383909 Forming aluminum oxide on aluminum or aluminum alloy wiring by baking with water; improves bonding of wires to aluminum wiring |
| 05/07/2002 | US6383907 Process for fabricating a semiconductor device |
| 05/07/2002 | US6383906 Method of forming junction-leakage free metal salicide in a semiconductor wafer with ultra-low silicon consumption |
| 05/07/2002 | US6383905 Formation of micro rough poly surface for low sheet resistance salicided sub-quarter micron poly lines |
| 05/07/2002 | US6383904 Fabrication of self-aligned front gate and back gate of a field effect transistor in semiconductor on insulator |
| 05/07/2002 | US6383903 Method for forming the partial salicide |
| 05/07/2002 | US6383902 Method for producing a microelectronic semiconductor component |
| 05/07/2002 | US6383901 Method for forming the ultra-shallow junction by using the arsenic plasma |
| 05/07/2002 | US6383900 Method and apparatus for forming polycrystal silicon film |
| 05/07/2002 | US6383899 Method of forming polycrystalline semiconductor film from amorphous deposit by modulating crystallization with a combination of pre-annealing and ion implantation |
| 05/07/2002 | US6383898 Method for manufacturing photoelectric conversion device |
| 05/07/2002 | US6383897 Apparatus for manufacturing a semiconductor device in a CVD reactive chamber |
| 05/07/2002 | US6383895 Method of forming a plurality of semiconductor devices |
| 05/07/2002 | US6383894 Method of forming scribe line planarization layer |
| 05/07/2002 | US6383893 Method of forming a crack stop structure and diffusion barrier in integrated circuits |
| 05/07/2002 | US6383892 Double silicon-on-insulator device and method thereof |
| 05/07/2002 | US6383891 Method for forming bump and semiconductor device |
| 05/07/2002 | US6383890 Wafer bonding method, apparatus and vacuum chuck |
| 05/07/2002 | US6383889 Semiconductor device having improved parasitic capacitance and mechanical strength |
| 05/07/2002 | US6383887 Methods of forming capacitors, DRAM arrays, and monolithic integrated circuits |
| 05/07/2002 | US6383886 Frming insulative material layer having an upper surface and container opening; providing first conductive layer over insulative material; providing fill layer material over first conductive layer; removing portions of fill layer |
| 05/07/2002 | US6383885 Bipolar transistor with improved reverse breakdown characteristics |
| 05/07/2002 | US6383884 Method of manufacturing semiconductor device |
| 05/07/2002 | US6383883 Method of reducing junction capacitance of source/drain region |
| 05/07/2002 | US6383882 Method for fabricating MOS transistor using selective silicide process |
| 05/07/2002 | US6383881 Method for using thin spacers and oxidation in gate oxides |
| 05/07/2002 | US6383880 NH3/N2-plasma treatment for reduced nickel silicide bridging |
| 05/07/2002 | US6383879 Semiconductor device having a metal gate with a work function compatible with a semiconductor device |
| 05/07/2002 | US6383878 Method of integrating a salicide process and a self-aligned contact process |
| 05/07/2002 | US6383877 Method of forming T-shaped isolation layer, method of forming elevated salicide source/drain region using the same, and semiconductor device having T-shaped isolation layer |
| 05/07/2002 | US6383876 MOS device having non-uniform dopant concentration and method for fabricating the same |
| 05/07/2002 | US6383875 Vapor depositing silicon nitride over electrode in borophosphorosilicate, oxidizing to form silicon dioxide, and forming a second electrode; silicon nitride prevents reoxidation of bpsg even when below 80 angstroms |
| 05/07/2002 | US6383874 In-situ stack for high volume production of isolation regions |
| 05/07/2002 | US6383873 Process for forming a structure |
| 05/07/2002 | US6383872 Parallel and series-coupled transistors having gate conductors formed on sidewall surfaces of a sacrificial structure |
| 05/07/2002 | US6383871 Method of forming multiple oxide thicknesses for merged memory and logic applications |
| 05/07/2002 | US6383870 Semiconductor device architectures including UV transmissive nitride layers |
| 05/07/2002 | US6383869 Side wall contact structure and method of forming the same |
| 05/07/2002 | US6383868 Methods for forming contact and container structures, and integrated circuit devices therefrom |
| 05/07/2002 | US6383867 Method of manufacturing semiconductor memory device |
| 05/07/2002 | US6383866 Semiconductor device and manufacturing method thereof |
| 05/07/2002 | US6383865 Fabricating a capacitor having a bottom electrode, of which an upper part is smaller than a lower part; multiple oxide layers; wet etching; dry etching |
| 05/07/2002 | US6383864 Memory cell for dynamic random access memory (DRAM) |
| 05/07/2002 | US6383863 Approach to integrate salicide gate for embedded DRAM devices |
| 05/07/2002 | US6383862 Method of forming a contact hole in a semiconductor substrate using oxide spacers on the sidewalls of the contact hole |
| 05/07/2002 | US6383861 Method of fabricating a dual gate dielectric |
| 05/07/2002 | US6383860 Semiconductor device and method of manufacturing the same |
| 05/07/2002 | US6383859 Method of forming semiconductor device including patterning lower electrode of capacitor and gate electrode of transistor with same resist |
| 05/07/2002 | US6383858 Interdigitated capacitor structure for use in an integrated circuit |
| 05/07/2002 | US6383857 Semiconductor device and method for manufacturing the same |
| 05/07/2002 | US6383856 Semiconductor device and method for manufacturing the same |
| 05/07/2002 | US6383855 High speed, low cost BICMOS process using profile engineering |
| 05/07/2002 | US6383853 Method of fabricating semiconductor device |
| 05/07/2002 | US6383852 Semiconductor device and fabrication method thereof |
| 05/07/2002 | US6383851 Converting amorphous silicon layer into a hemispherical grained silicon film |
| 05/07/2002 | US6383850 Semiconductor device and method of manufacturing the same |
| 05/07/2002 | US6383849 Semiconductor device and method for fabricating the same |
| 05/07/2002 | US6383848 Method of isolating a SRAM cell |
| 05/07/2002 | US6383847 Partitioned mask layout |
| 05/07/2002 | US6383846 Method and apparatus for molding a flip chip semiconductor device |
| 05/07/2002 | US6383844 Multi-chip bonding method and apparatus |
| 05/07/2002 | US6383843 Using removable spacers to ensure adequate bondline thickness |
| 05/07/2002 | US6383842 Method for producing semiconductor device having increased adhesion between package and semiconductor chip bottom |
| 05/07/2002 | US6383841 Method for encapsulating with a fixing member to secure an electronic device |
| 05/07/2002 | US6383840 Semiconductor device, method of manufacture thereof, circuit board, and electronic device |
| 05/07/2002 | US6383838 Substrateless chip scale package and method of making same |