Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
07/2002
07/18/2002WO2002056339A2 Point contacts for semiconductors and the production thereof
07/18/2002WO2002056338A2 Device for the plasma-mediated working of surfaces on planar substrates
07/18/2002WO2002056337A1 Chromium adhesion layer for copper vias in low-k technology
07/18/2002WO2002056333A1 Plasma processing apparatus
07/18/2002WO2002056114A2 Projection system for euv lithography
07/18/2002WO2002056113A2 Method for producing an etching mask
07/18/2002WO2002056101A1 Contact structure of substrates of touch panel and method of bonding the same
07/18/2002WO2002056046A1 Device for detecting a magnetic field, magnetic field measurer and current meter
07/18/2002WO2002056040A1 Pusher and electronic part tester with the pusher
07/18/2002WO2002056036A2 Method for characterization of ldmos devices at the die reference plane
07/18/2002WO2002055938A1 Device and method for feeding treating air
07/18/2002WO2002055762A2 Electrochemical co-deposition of metals for electronic device manufacture
07/18/2002WO2002055757A1 Liquid distribution unit for dividing a liquid current into a plurality of partial currents
07/18/2002WO2002055756A1 Apparatus for exhaust whie powder elimination in substrate processing
07/18/2002WO2002055458A2 Process for purifying octafluorocyclobutane, process for preparing the same, and use thereof
07/18/2002WO2002055414A1 Handling apparatus & method for a lead frame processing system
07/18/2002WO2002055392A2 Apparatus and method for transporting a container
07/18/2002WO2002055259A2 Tantalum removal during chemical mechanical processing
07/18/2002WO2002043112A3 Method for making a substrate
07/18/2002WO2002039488A3 Method for producing an integrated circuit
07/18/2002WO2002035559A3 Magnetic layer formed of multiple sub-element layers
07/18/2002WO2002031877A8 Specimen analyzing method
07/18/2002WO2002031864A9 Monolithic lead-salt infrared detectors
07/18/2002WO2002027405A3 Illumination system particularly for microlithography
07/18/2002WO2002023119A8 Determination of a wafer notch/cam position (in the transport path) with reflected edge light
07/18/2002WO2002017356A3 Method and structure for adhering msq material to liner oxide
07/18/2002WO2002011208A3 Method for fabrication of on-chip inductors and related structure
07/18/2002WO2002009147A3 High pressure processing chamber for semiconductor substrate
07/18/2002WO2002008836A3 Method and device for thermally treating a photoresist layer on a circuit substrate, especially a semiconductor wafer
07/18/2002WO2002007931A3 Multi-chamber carrier head with a flexible membrane
07/18/2002WO2002007205A3 Etching composition and use thereof for cleaning metallization layers
07/18/2002WO2002007198A3 Deposition of low stress tantalum films
07/18/2002WO2002007166A3 Mram architectures for increased write selectivity
07/18/2002WO2001099162A3 Gate oxidation for vertical trench device
07/18/2002WO2001093331A3 Fuse link
07/18/2002WO2001091180A3 System and method of forming a vertically oriented device in an integrated circuit
07/18/2002WO2001091177A3 Method and apparatus for controlling deposition parameters based on polysilicon grain size feedback
07/18/2002WO2001088976A3 Wireless radio frequency testing methode of integrated circuits and wafers
07/18/2002WO2001084599A3 Uv-enhanced silylation process to increase etch resistance of ultra thin resists
07/18/2002WO2001082380A3 Power semiconductor device having a trench gate electrode and method of making the same
07/18/2002WO2001082341B1 Thermal processing system and thermal processing method
07/18/2002WO2001081856A3 Technique for determining curvatures of embedded line features on substrates
07/18/2002WO2001080306A3 Automated process monitoring and analysis system for semiconductor processing
07/18/2002WO2001078154A3 Preparation of cigs-based solar cells using a buffered electrodeposition bath
07/18/2002WO2001075973A3 Combined transistor-capacitor structure in deep sub-micron cmos for power amplifiers
07/18/2002WO2001061735A3 Implantation mask for high energy ion implantation
07/18/2002WO2000067327A9 Minimally-patterned semiconductor devices for display applications
07/18/2002US20020095649 Optimized emulation and prototyping architecture
07/18/2002US20020095648 Layout method of analog/digital mixed semiconductor integrated circuit
07/18/2002US20020095647 Method for adding decoupling capacitance during integrated circuit design
07/18/2002US20020095643 Method and apparatus for revising wiring of a circuit to prevent electro-migration
07/18/2002US20020095631 Input/output continuity test mode circuit
07/18/2002US20020095278 Method for adjusting rapid thermal processing (RTP) recipe setpoints based on wafer electrical test (WET) parameters
07/18/2002US20020095273 Method of extracting physical model parameter and storage medium therefor, and method of manufacturing non-linear element
07/18/2002US20020095223 Stocker apparatus affording manual access
07/18/2002US20020095192 Method of fabricating a flip-chip ball-grid-array package with molded underfill
07/18/2002US20020095018 Comprising silicon-based compound and incorporatable organic absorbing compound that absorbs light at a wavelength less than 375 nm, wherein one of the silicon or absorber compounds comprises an alkyl, an alkoxy, a ketone, or an azo group
07/18/2002US20020094940 Cleaning method to remove flux residue in electronic assembly
07/18/2002US20020094767 Carrier head with multi-part flexible membrane
07/18/2002US20020094766 Carrier head with a substrate sensor
07/18/2002US20020094763 Rotary drive device of a polishing device
07/18/2002US20020094760 Protective film separator in semiconductor wafer grinding process
07/18/2002US20020094707 Electronic configuration with flexible bonding pads
07/18/2002US20020094699 Substrate comprises a buffer layer and a channel layer, silicon oxide is formed on the channel by a liquid phase deposition to control the parameters of the gallium arsenide
07/18/2002US20020094698 Inserting a layer of silicon nitride under substantial compressive stress between low k dielectric black diamond and a substrate
07/18/2002US20020094697 DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same
07/18/2002US20020094696 Multiple loadlock system
07/18/2002US20020094695 Mixed gases containing perfluorobutane and oxygen or tetrafluorocarbon, trifluoromethane and nitrogen are used to carry out via hole etching
07/18/2002US20020094694 Bombarding in a vacuum a portion of the substrate with a focused particle beam from a particle source, and exposing the substrate to an organic chloride or hydroxide
07/18/2002US20020094693 Method for fabricating an ultra small opening
07/18/2002US20020094692 Method for carrying out a plasma etching process
07/18/2002US20020094691 Method for manufacturing semiconductor device
07/18/2002US20020094690 Method for dry etching deep trenches in a substrate
07/18/2002US20020094689 Apparatus and method for depositing thin film on wafer using atomic layer deposition
07/18/2002US20020094688 Method of forming fine patterns
07/18/2002US20020094687 Method of fabricating semiconductor device for preventing contaminating particle generation
07/18/2002US20020094685 Semiconductor manufacturing methods, plasma processing methods and plasma processing apparatuses
07/18/2002US20020094684 Foam cleaning process in semiconductor manufacturing
07/18/2002US20020094683 Method for manufacturing chip size package and its structure
07/18/2002US20020094682 Reactor and a susceptorr is coated with an aluminum gallium indium nitride, which is heated to >/= 1000 degress C to generate chemical vapor deposition between a III and a V raw material gases
07/18/2002US20020094681 In-situ monitoring of chemical vapor deposition process by mass spectrometry
07/18/2002US20020094680 Unlanded process in semiconductor manufacture
07/18/2002US20020094679 Alignment mark and exposure alignment system and method using the same
07/18/2002US20020094678 Process for fabricating a single-crystal substrate and integrated circuit comprising such a substrate
07/18/2002US20020094677 Semiconductor laser and method of manufacturing the same
07/18/2002US20020094676 Salicide integrated solution for embedded virtual-ground memory
07/18/2002US20020094675 Methods of contacting lines and methods of forming an electrical contact in a semiconductor device
07/18/2002US20020094674 Methods for inhibiting microelectronic damascene processing induced low dielectric constant dielectric layer physical degradation
07/18/2002US20020094673 Method for making interconnects and diffusion barriers in integrated circuits
07/18/2002US20020094671 Methods for providing void-free layers for semiconductor assemblies
07/18/2002US20020094670 Semiconductor device having bonding pad electrode of multi-layer structure
07/18/2002US20020094669 Semiconductor device having reduced contact resistance and leakage and method of construction
07/18/2002US20020094668 Thin layer structure made up of conductive and insulative zones
07/18/2002US20020094667 Semiconductor device and a method for production thereof
07/18/2002US20020094666 Method of providing a frontside contact to a substrate of SOI device
07/18/2002US20020094665 Method for manufacturing an SOI wafer
07/18/2002US20020094664 Method and apparatus for removal of surface contaminants from substrates in vacuum applications
07/18/2002US20020094663 Method of manufacturing an SOI (silicon on insulator ) wafer
07/18/2002US20020094662 Method and device for protecting micro electromechanical systems structures during dicing of a wafer
07/18/2002US20020094661 Three dimensional device intergration method and intergrated device