Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
07/2002
07/24/2002EP0946971B1 Substrate treatment device
07/24/2002EP0827631B1 Process for structuring porous silicon
07/24/2002EP0707742B1 Process for forming a metallic interconnect structure for integrated circuits
07/24/2002CN2502404Y Mould pressing tool for preventing glue-spilling semicondcutor encapsulating die press
07/24/2002CN2502403Y Semiconductor programming equipment with working piece transmitting protective function
07/24/2002CN1360815A Underfilling material for semiconductor package
07/24/2002CN1360738A Power MOSFET and method of making same
07/24/2002CN1360736A Chip holder for chip module and method for producing said chip module
07/24/2002CN1360735A Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating same
07/24/2002CN1360734A Method of mfg. semiconductor device
07/24/2002CN1360733A Process for removing contaminant from surface and composition useful therefor
07/24/2002CN1360559A Low-permittivity porous siliceous film, semiconductor devices having such films, and coating composition for forming film
07/24/2002CN1360536A Corrosion resistant exoskeleton arm linkage assembly
07/24/2002CN1360383A Equipment with charging function and able to output more voltages
07/24/2002CN1360349A Device having thin film transistor
07/24/2002CN1360348A Structure and circuit of logarithmic skip adder
07/24/2002CN1360346A 电子结构及其形成方法 Electronic structure and method of forming
07/24/2002CN1360345A Processing system for cutting semiconductor packing device
07/24/2002CN1360344A Method of mfg. semiconductor device, and semiconductor device
07/24/2002CN1360343A Method for generating extended super-shallow source-drain region by combining amorphous pre-injection of Ge with low energy injection
07/24/2002CN1360342A Method for realizing technological section structure of 70-nm device
07/24/2002CN1360341A Titanium silicide method using amorphous pre-injection of Ge or Sb and washing
07/24/2002CN1360340A Auto-aligning method for Co to silicide
07/24/2002CN1360339A Method and device for searching flaw aggregation in mfg. semiconductor device, and program thereby
07/24/2002CN1360338A 半导体器件 Semiconductor devices
07/24/2002CN1360178A Purifying chamber and semiconductor device mfg. method
07/24/2002CN1360088A Etching-fluorination plus reaction ion etching process for preparing 70-nm polysilicon grid
07/24/2002CN1359998A Acidic polishing cream for chemicomechanically polishing SiO2 isolating layer
07/24/2002CN1359997A Polishing cream for polishing silicon dioxide film by chemicomechanical process
07/24/2002CN1359784A Method and device for dividing brittle substrate
07/24/2002CN1088261C Silicon-on-insulator device with floating collector
07/24/2002CN1088260C Active matrix electro-optical device
07/24/2002CN1088259C Method for mfg. semiconductor device having oxide film of high quality on semiconductor substrate
07/24/2002CN1088258C Crystal wafer temp. on-situ controler for single wafer tool
07/24/2002CN1088257C Fabrication method of semiconductor device
07/24/2002CN1088256C Method of producing ohmic contact and semiconductor device provided with said ohmic contact
07/24/2002CN1088255C Method for producing semiconductor device
07/24/2002CN1088109C Method and composition for determination of sodium ions in fluids
07/24/2002CN1088070C Novel amide- and imide-contg. copolymer, preparation thereof and photoresist comprising same
07/23/2002US6425117 System and method for performing optical proximity correction on the interface between optical proximity corrected cells
07/23/2002US6425092 Method and apparatus for preventing thermal failure in a semiconductor device through redundancy
07/23/2002US6425048 Memory pool control circuit and memory pool control method
07/23/2002US6425046 Method for using a latched sense amplifier in a memory module as a high-speed cache memory
07/23/2002US6424881 Computer generated recipe selector utilizing defect file information
07/23/2002US6424880 Multi-computer chamber control system, method and medium
07/23/2002US6424879 System and method to correct for distortion caused by bulk heating in a substrate
07/23/2002US6424733 Method and apparatus for inspecting wafers
07/23/2002US6424588 Semiconductor memory device capable of realizing a chip with high operation reliability and high yield
07/23/2002US6424573 Floating gate field effect transistor and method of driving the same
07/23/2002US6424568 Code addressable memory cell in flash memory device
07/23/2002US6424565 Solid-state memory with magnetic storage cells
07/23/2002US6424564 MRAM architectures for increased write selectivity
07/23/2002US6424563 MRAM memory cell
07/23/2002US6424562 Read/write architecture for MRAM
07/23/2002US6424561 MRAM architecture using offset bits for increased write selectivity
07/23/2002US6424558 Ferroelectric memory array composed of a multiplicity of memory cells each having at least one selection transistor and one storage capacitor driven via word lines and bit lines
07/23/2002US6424557 Integrated device with trimming elements
07/23/2002US6424509 Semiconductor including a protective circuit
07/23/2002US6424471 Catadioptric objective with physical beam splitter
07/23/2002US6424405 Exposure apparatus and device manufacturing method
07/23/2002US6424326 Semiconductor display device having a display portion and a sensor portion
07/23/2002US6424232 Method and apparatus for matching a variable load impedance with an RF power generator impedance
07/23/2002US6424201 Diode element circuit and switch circuit using the same
07/23/2002US6424171 Base cell and two-dimensional array of base cells for programmable logic LSI
07/23/2002US6424168 Reduced terminal testing system
07/23/2002US6424137 Use of acoustic spectral analysis for monitoring/control of CMP processes
07/23/2002US6424134 Semiconductor integrated circuit device capable of stably generating internal voltage independent of an external power supply voltage
07/23/2002US6424128 Electronic device having power supply regulators controlled according to operation mode of internal circuit
07/23/2002US6424052 Alignment mark for electron beam lithography
07/23/2002US6424051 Semiconductor device
07/23/2002US6424050 Semiconductor device
07/23/2002US6424049 Semiconductor device having chip-on-chip structure and semiconductor chip used therefor
07/23/2002US6424048 Semiconductor chip, semiconductor device, circuit board and electronic equipment and production methods for them
07/23/2002US6424045 Semiconductor device with pure copper wirings and method of manufacturing a semiconductor device with pure copper wirings
07/23/2002US6424044 Plasma enhanced vapor deposition
07/23/2002US6424043 Semiconductor processing methods of forming integrated circuitry memory devices, methods of forming capacitor containers, methods of making electrical connection to circuit nodes and related integrated circuitry
07/23/2002US6424042 Semiconductor device and manufacturing method thereof
07/23/2002US6424041 Semiconductor device
07/23/2002US6424039 Dual damascene process using sacrificial spin-on materials
07/23/2002US6424037 Process to make a tall solder ball by placing a eutectic solder ball on top of a high lead solder ball
07/23/2002US6424036 Semiconductor device and method for manufacturing the same
07/23/2002US6424033 Chip package with grease heat sink and method of making
07/23/2002US6424032 Semiconductor device having a power supply ring and a ground ring
07/23/2002US6424028 Semiconductor devices configured to tolerate connection misalignment
07/23/2002US6424021 Passivation method for copper process
07/23/2002US6424020 High Density electronic circuit modules
07/23/2002US6424019 Shallow trench isolation chemical-mechanical polishing process
07/23/2002US6424016 SOI DRAM having P-doped polysilicon gate for a memory pass transistor
07/23/2002US6424015 Semiconductor integrated circuit device
07/23/2002US6424014 Semiconductor element with electric field reducing device mounted therein for increasing dielectric strength
07/23/2002US6424012 Semiconductor device having a tantalum oxide blocking film
07/23/2002US6424011 Mixed memory integration with NVRAM, dram and sram cell structures on same substrate
07/23/2002US6424010 Method of manufacturing a semiconductor device having reduced power consumption without a reduction in the source/drain breakdown voltage
07/23/2002US6424009 Polysilicon insulator material in semiconductor-on-insulator (SOI) structure
07/23/2002US6424008 Memory device having a floating gate
07/23/2002US6424007 High-voltage transistor with buried conduction layer
07/23/2002US6424006 Semiconductor component
07/23/2002US6424005 LDMOS power device with oversized dwell
07/23/2002US6424004 Agglomeration by annealing
07/23/2002US6424002 Transistor, transistor array and non-volatile semiconductor memory