Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
07/2002
07/30/2002US6426554 Semiconductor device
07/30/2002US6426552 Methods employing hybrid adhesive materials to secure components of semiconductor device assemblies and packages to one another and assemblies and packages including components secured to one another with such hybrid adhesive materials
07/30/2002US6426548 Semiconductor device, lead-patterning substrate, and electronics device, and method for fabricating same
07/30/2002US6426544 Flexible interconnections with dual-metal dual-stud structure
07/30/2002US6426543 Semiconductor device including high-frequency circuit with inductor
07/30/2002US6426542 Schottky diode with dielectric trench
07/30/2002US6426541 Schottky diode having increased forward current with improved reverse bias characteristics and method of fabrication
07/30/2002US6426536 Double layer perovskite oxide electrodes
07/30/2002US6426535 Semiconductor device having improved short channel resistance
07/30/2002US6426533 Semiconductor device and manufacturing method thereof
07/30/2002US6426532 Semiconductor device and method of manufacture thereof
07/30/2002US6426531 Semiconductor integrated circuit device and a method of assembly thereof
07/30/2002US6426530 High performance direct coupled FET memory cell
07/30/2002US6426529 Semiconductor memory
07/30/2002US6426528 Method of fabricating conductive straps to interconnect contacts to corresponding digit lines by employing an angled sidewall implant and semiconductor devices fabricated thereby
07/30/2002US6426527 Semiconductor memory and method for fabricating the same
07/30/2002US6426526 Single sided buried strap
07/30/2002US6426525 FET structures having symmetric and/or distributed feedforward capacitor connections
07/30/2002US6426524 Fabricating a square spacer
07/30/2002US6426523 Intermetallics; dry gas etching
07/30/2002US6426522 Doped semiconductor material, a method of manufacturing the doped semiconductor material, and a semiconductor device
07/30/2002US6426519 Epitaxial growth substrate and a method for producing the same
07/30/2002US6426508 Surface-position detection device, a projection exposure apparatus using the device, and a device manufacturing method using the apparatus
07/30/2002US6426502 Apparatus for integrated monitoring of wafers and for process control in the semiconductor manufacturing and a method for use thereof
07/30/2002US6426499 Multi-probe test head and process using same
07/30/2002US6426486 Optical apparatus and method for shrinking heat shrink tubing, fusing wires and solder and unsolder packaged electronic components
07/30/2002US6426484 Circuit and method for heating an adhesive to package or rework a semiconductor die
07/30/2002US6426478 Planarization using laser ablation
07/30/2002US6426477 Plasma processing method and apparatus for eliminating damages in a plasma process of a substrate
07/30/2002US6426467 Film carrier with adjacent electrical sorting pads
07/30/2002US6426460 Velcro strapping for semiconductor carrying trays
07/30/2002US6426308 Methods for forming films having high dielectric constants
07/30/2002US6426307 Ammonia activation gas is delivered into a reactor at the same time as trimethylaluminum and using methanol, ethanol or isopropanol as oxygen source instead of water vapor
07/30/2002US6426306 Barrier layer fabrication methods
07/30/2002US6426305 Patterned plasma nitridation for selective epi and silicide formation
07/30/2002US6426304 Forming reducing plasma in reaction vessel in proximity with portion of semiconductor wafer including layer of organosilicate dielectric, using plasma to strip portion of photoresist from wafer in situ within semiconductor apparatus
07/30/2002US6426303 Processing system
07/30/2002US6426302 Useful for continuously producing negative ions in high density and also negative ions can be made incident on the semiconductor substrate to be processed to conduct ashing, etching and cleaning of the substrate to remove impurities
07/30/2002US6426301 Reduction of via etch charging damage through the use of a conducting hard mask
07/30/2002US6426300 Method for fabricating semiconductor device by using etching polymer
07/30/2002US6426299 Method and apparatus for manufacturing semiconductor device
07/30/2002US6426298 Method of patterning a dual damascene
07/30/2002US6426297 Differential pressure chemical-mechanical polishing in integrated circuit interconnects
07/30/2002US6426296 Method and apparatus for obtaining a precision thickness in semiconductor and other wafers
07/30/2002US6426294 Polishing conductive material film comprising copper or copper alloy using aqueous composition comprising pyridine-based carboxylic acid and acid having one carboxyl and one hydroxyl group or oxalic acid, abrasive grains and oxidizing agent
07/30/2002US6426293 Minimizing resistance and electromigration of interconnect by adjusting anneal temperature and amount of seed layer dopant
07/30/2002US6426292 Methods for forming iridium and platinum containing films on substrates
07/30/2002US6426291 Method of co-deposition to form ultra-shallow junctions in MOS devices using electroless or electrodeposition
07/30/2002US6426289 Method of fabricating a barrier layer associated with a conductor layer in damascene structures
07/30/2002US6426288 Method for removing an upper layer of material from a semiconductor wafer
07/30/2002US6426286 Interconnection system with lateral barrier layer
07/30/2002US6426285 Method to solve intermetallic dielectric cracks in integrated circuit devices
07/30/2002US6426283 Method for bumping and backlapping a semiconductor wafer
07/30/2002US6426282 Method of forming solder bumps on a semiconductor wafer
07/30/2002US6426281 Method to form bump in bumping technology
07/30/2002US6426280 Method for doping spherical semiconductors
07/30/2002US6426279 Epitaxial delta doping for retrograde channel profile
07/30/2002US6426278 Projection gas immersion laser dopant process (PGILD) fabrication of diffusion halos
07/30/2002US6426277 Methods and a device for heat treating a semiconductor wafer having different kinds of impurities
07/30/2002US6426276 Forming amorphous semiconductor film containing silicon on substrate with insulating surface, introducing elements that promote crystallization, crystallizing through heat treatment, introducing elements that getter catalysts, activating
07/30/2002US6426275 Method for manufacturing semiconductor chips using protecting pricing and separating sheets
07/30/2002US6426274 Method for making thin film semiconductor
07/30/2002US6426273 Preprocessing method of metal film forming process
07/30/2002US6426272 Method to reduce STI HDP-CVD USG deposition induced defects
07/30/2002US6426271 Forming a pad insulating a mask layer on a semiconductor substrate,patterning both layers and etching the substrate using both layers as etch mask to form trench, using hydrogen fluoride and oxidizer to round the trench edge
07/30/2002US6426270 Substrate processing method and method of manufacturing semiconductor substrate
07/30/2002US6426268 Thin film resistor fabrication method
07/30/2002US6426267 Method for fabricating high-Q inductance device in monolithic technology
07/30/2002US6426266 Manufacturing method for an inverted-structure bipolar transistor with improved high-frequency characteristics
07/30/2002US6426265 Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology
07/30/2002US6426264 Method of manufacturing a semiconductor laminated substrate, semiconductor crystal substrate and semiconductor device
07/30/2002US6426263 Method for making a merged contact window in a transistor to electrically connect the gate to either the source or the drain
07/30/2002US6426262 Method of analyzing the effects of shadowing of angled halo implants
07/30/2002US6426261 Logic circuit and its fabrication method
07/30/2002US6426260 Switching speed improvement in DMO by implanting lightly doped region under gate
07/30/2002US6426259 Vertical field effect transistor with metal oxide as sidewall gate insulator
07/30/2002US6426258 Method of manufacturing a semiconductor integrated circuit device
07/30/2002US6426257 Flash memory and manufacturing method therefor
07/30/2002US6426256 Method for fabricating an embedded DRAM with self-aligned borderless contacts
07/30/2002US6426255 Forming lower electrode film of platinum metal, platinum alloy or conductive oxide of platinum metal with pattern of such accuracy that amount of accumulative charge of information storing capacitor is maintained on miniaturization of cell
07/30/2002US6426254 Method for expanding trenches by an anisotropic wet etch
07/30/2002US6426253 Method of forming a vertically oriented device in an integrated circuit
07/30/2002US6426252 Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap
07/30/2002US6426251 Process for manufacturing a crystal axis-aligned vertical side wall device
07/30/2002US6426250 High density stacked MIM capacitor structure
07/30/2002US6426249 Buried metal dual damascene plate capacitor
07/30/2002US6426248 Process for forming power MOSFET device in float zone, non-epitaxial silicon
07/30/2002US6426247 Low bitline capacitance structure and method of making same
07/30/2002US6426246 Method for forming thin film transistor with lateral crystallization
07/30/2002US6426245 Method for manufacturing a semiconductor device
07/30/2002US6426244 Process of forming a thick oxide field effect transistor
07/30/2002US6426243 Methods of forming dynamic random access memory circuitry
07/30/2002US6426242 Semiconductor chip packaging method
07/30/2002US6426241 Method for forming three-dimensional circuitization and circuits formed
07/30/2002US6426238 Charge transfer device and solid image pickup apparatus using the same
07/30/2002US6426237 Method for producing optically planar surfaces for micro-electromechanical system devices
07/30/2002US6426235 Method of manufacturing semiconductor device
07/30/2002US6426234 Silicon tip anodized by ultravolet radiation; resulting oxide layer removed using hydrogen halide; results in sharpened tip
07/30/2002US6426232 Optical techniques of measuring endpoint during the processing of material layers in an optically hostile environment
07/30/2002US6426176 Forming metal bump of first material on substrate so that bump electrically contacts metal part on substrate, forming protective layer on metal bump which has higher conductivity than first material