| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 09/03/2002 | US6445050 Symmetric device with contacts self aligned to gate |
| 09/03/2002 | US6445048 Semiconductor configuration having trenches for isolating doped regions |
| 09/03/2002 | US6445047 Semiconductor device and method for fabricating the same |
| 09/03/2002 | US6445046 Memory cell arrangement and process for manufacturing the same |
| 09/03/2002 | US6445045 Low resistivity titanium silicide structures |
| 09/03/2002 | US6445044 Apparatus improving latchup immunity in a dual-polysilicon gate |
| 09/03/2002 | US6445043 Isolated regions in an integrated circuit |
| 09/03/2002 | US6445042 Method and apparatus for making MOSFETs with elevated source/drain extensions |
| 09/03/2002 | US6445041 Semiconductor memory cell array with reduced parasitic capacitance between word lines and bit lines |
| 09/03/2002 | US6445040 Lateral bipolar type input/output protection device |
| 09/03/2002 | US6445038 Silicon on insulator high-voltage switch |
| 09/03/2002 | US6445037 Trench DMOS transistor having lightly doped source structure |
| 09/03/2002 | US6445036 Semiconductor device having trench-structured rectangular unit cells |
| 09/03/2002 | US6445035 Power MOS device with buried gate and groove |
| 09/03/2002 | US6445033 Gate-insulating film including oxide film |
| 09/03/2002 | US6445032 Floating back gate electrically erasable programmable read-only memory(EEPROM) |
| 09/03/2002 | US6445031 Byte-switch structure for EEPROM memories |
| 09/03/2002 | US6445030 Flash memory erase speed by fluorine implant or fluorination |
| 09/03/2002 | US6445029 NVRAM array device with enhanced write and erase |
| 09/03/2002 | US6445028 Semiconductor device and method of fabricating the same |
| 09/03/2002 | US6445027 Multilayer; vapor deposition; tantalum oxynitride |
| 09/03/2002 | US6445026 Semiconductor device having a memory cell with a plurality of active elements and at least one passive element |
| 09/03/2002 | US6445025 Semiconductor memory device and manufacturing method thereof |
| 09/03/2002 | US6445023 Diffusion barriers |
| 09/03/2002 | US6445018 Semiconductor device having signal line above main ground or main VDD line, and manufacturing method thereof |
| 09/03/2002 | US6445017 Full CMOS SRAM cell |
| 09/03/2002 | US6445016 Silicon-on-insulator (SOI) transistor having partial hetero source/drain junctions fabricated with high energy germanium implantation |
| 09/03/2002 | US6445015 Metal sulfide semiconductor transistor devices |
| 09/03/2002 | US6445014 Retrograde well structure for a CMOS imager |
| 09/03/2002 | US6445012 Semiconductor device and manufacturing method thereof |
| 09/03/2002 | US6445004 Composition for a wiring, a wiring using the composition, manufacturing method thereof, a display using the wiring and a manufacturing method thereof |
| 09/03/2002 | US6445002 SRAM-based semiconductor integrated circuit testing element |
| 09/03/2002 | US6445001 Semiconductor device with flip-chip structure and method of manufacturing the same |
| 09/03/2002 | US6444995 Focussing method and system of exposure apparatus |
| 09/03/2002 | US6444974 Method for transferring a dummy wafer |
| 09/03/2002 | US6444957 Heating apparatus |
| 09/03/2002 | US6444940 Heat treating device and heat treating method |
| 09/03/2002 | US6444921 Reduced stress and zero stress interposers for integrated-circuit chips, multichip substrates, and the like |
| 09/03/2002 | US6444918 Interconnection structure of semiconductor element |
| 09/03/2002 | US6444905 Semiconductor device |
| 09/03/2002 | US6444899 Solar cell and method of fabricating the same |
| 09/03/2002 | US6444895 Irradiation surfaces with laser beams; nondeforming detection of defects |
| 09/03/2002 | US6444715 Low dielectric materials and methods of producing same |
| 09/03/2002 | US6444593 Depleting fluorine from surface of fluorinated silicon dioxide dielectric material disposed between first metal stack and second metal stack utilizing ammonia, passivating surface utilizing nitrous oxide |
| 09/03/2002 | US6444592 Interfacial oxidation process for high-k gate dielectric process integration |
| 09/03/2002 | US6444591 Method for reducing contamination prior to epitaxial growth and related structure |
| 09/03/2002 | US6444590 Semiconductor processing methods, methods of forming hemispherical grain polysilicon, methods of forming capacitors, and methods of forming wordlines |
| 09/03/2002 | US6444589 Method and apparatus for etching silicon |
| 09/03/2002 | US6444588 Providing inorganic silicon oxynitride antireflective coating material layer on substrate assembly surface, using layer in photolithographic process, thermally treating layer to reduce etch rate |
| 09/03/2002 | US6444587 Plasma etching microelectronic layer on substrate within plasma reactor chamber, transferring substrate to load lock chamber integral with plasma reactor chamber, purging load lock chamber with inert gas, removing substrate from chamber |
| 09/03/2002 | US6444586 Method of etching doped silicon dioxide with selectivity to undoped silicon dioxide with a high density plasma etcher |
| 09/03/2002 | US6444585 Plasma etching conductive layer on semiconductor substrate using argon ions to remove natural oxide, heating at specified temperature to expel argon atoms from conductive layer, forming second conductive layer on first layer by sputtering |
| 09/03/2002 | US6444584 Plasma etch method for forming composite silicon/dielectric/silicon stack layer |
| 09/03/2002 | US6444583 Substrate-cleaning method and substrate-cleaning solution |
| 09/03/2002 | US6444582 Immersing substrate having silicon oxynitride layer in solution of ethylene glycol and hydrogen fluoride at specified temperature |
| 09/03/2002 | US6444581 AB etch endpoint by ABFILL compensation |
| 09/03/2002 | US6444580 Method of reducing carbon, sulphur, and oxygen impurities in a calcium-doped copper surface and semiconductor device thereby formed |
| 09/03/2002 | US6444579 Forming single implanted matrix comprising combination of group via and vb elements in layer of silicon, depositing titanium on implanted matrix, annealing to form titanium silicide |
| 09/03/2002 | US6444578 Forming layer of silicon, germanium, cobalt and/or nickel alloy over silicon-containing areas on wafer, annealing to form metal rich silicide, etching unreacted alloy, depositing silicon, annealing, removing unreacted silicon |
| 09/03/2002 | US6444577 Method of fabricating a semiconductor device having increased breakdown voltage |
| 09/03/2002 | US6444575 Completely etching through variable thickness masking layer and conformal isolation layer interposed between pair of topographic structures, not through layers over structures, to form pairs of patterned layers defining contact via |
| 09/03/2002 | US6444574 Method for forming stepped contact hole for semiconductor devices |
| 09/03/2002 | US6444573 Method of making a slot via filled dual damascene structure with a middle stop layer |
| 09/03/2002 | US6444572 Forming on electrically conductive material multi-level layer of masking material defining mask opening extending to and exposing conductive material, etching electrically conductive material through mask opening to form opening into conductor |
| 09/03/2002 | US6444571 Carrying out outgassing process at temperature that is not higher than deposition temperature of interlevel insulating layer |
| 09/03/2002 | US6444570 Method of manufacturing a multi-layered wiring structure for interconnecting semiconductor devices by patterning resist and antireflective films to define wiring grooves |
| 09/03/2002 | US6444569 Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process |
| 09/03/2002 | US6444568 Method of forming a copper diffusion barrier |
| 09/03/2002 | US6444567 Blanket-depositing layer of alloying element for metal feature on exposed upper surface of metal feature and dielectric layer, annealing to uniformly diffuse predetermined amount of alloying element into metal feature, removing excess |
| 09/03/2002 | US6444566 Introducing buffer layer of silicon oxynitride between silicon surface and silicon nitride layer used as etch stop layer |
| 09/03/2002 | US6444565 Dual-rie structure for via/line interconnections |
| 09/03/2002 | US6444564 Method and product for improved use of low k dielectric material among integrated circuit interconnect structures |
| 09/03/2002 | US6444563 Method and apparatus for extending fatigue life of solder joints in a semiconductor device |
| 09/03/2002 | US6444562 Nickel alloy films for reduced intermetallic formation in solder |
| 09/03/2002 | US6444561 Method for forming solder bumps for flip-chip bonding by using perpendicularly laid masking strips |
| 09/03/2002 | US6444560 Making connections between chips by using matching stud/via structures, fabricating device having dense arrangement of chips and high wiring density of chip-to-chip interconnections |
| 09/03/2002 | US6444559 Forming isolating film, gate insulating film, gate electrode, film spacer, source/drain regions, forming pad polycrystalline silicon layer pattern, forming contact plug using silicon pattern as seed, forming planarization film, contact hole |
| 09/03/2002 | US6444557 Providing substrate having insulative layer, depositing sacrificial conductive layer on insulative layer using physical vapor deposition, forming at least one circuit feature within insulative layer |
| 09/03/2002 | US6444556 Chemistry for chemical vapor deposition of titanium containing films |
| 09/03/2002 | US6444555 Establishing oxide base film having specified thickness on semiconductor substrate, annealing film in ammonia environment to form nitrided oxide film as ultra-thin insulator, forming polysilicon-based field effect transistor on film |
| 09/03/2002 | US6444554 Variation in threshold level of selective transistors is reduced when a shallow structure buried with an insulating film for element isolation is used |
| 09/03/2002 | US6444553 Junction formation with diffusion barrier for silicide contacts and method for forming |
| 09/03/2002 | US6444552 Method of reducing the conductivity of a semiconductor and devices made thereby |
| 09/03/2002 | US6444551 N-type buried layer drive-in recipe to reduce pits over buried antimony layer |
| 09/03/2002 | US6444550 Laser tailoring retrograde channel profile in surfaces |
| 09/03/2002 | US6444549 Thermal processing of semiconductor devices |
| 09/03/2002 | US6444548 Bitline diffusion with halo for improved array threshold voltage control |
| 09/03/2002 | US6444547 Epitaxially growing semiconductor layer having moderate crystal defects on sub-wafer with specified surface roughness, introducing impurities having different conductivity types to form pn junction, providing rapid thermal annealing |
| 09/03/2002 | US6444545 Including plurality of nanoclusters in trapping layer of traditional silicon-oxide-nitride-oxide-silicon structure improves charge retention, reliability characteristics and write/erase times |
| 09/03/2002 | US6444543 Forming semiconductor chips surrounded by peripheral grooves for separating into individual pieces on substrate surface, pasting protecting sheet on surface so sheet is bent along and adheres to bottom walls of grooves, dicing along grooves |
| 09/03/2002 | US6444542 Dielectric etching using halogen |
| 09/03/2002 | US6444541 Method for forming lining oxide in shallow trench isolation incorporating pre-annealing step |
| 09/03/2002 | US6444540 Semiconductor apparatus and method for fabricating the same |
| 09/03/2002 | US6444539 Layering areas between spaced apart dielectric pads that delineate u-shaped regions for forming shallow isolation trenches with silicon oxide and polysilicon, forming buffer that prevents erosion of pads during etch formation of trench |
| 09/03/2002 | US6444538 Forming carbon over active matrix; patterning |
| 09/03/2002 | US6444537 Depositing material to form electrode, depositing dielectric and organic material on electrode, depositing second material to form second electrode such that dielectric and organic material form layer between electrodes, isolating dielectric |
| 09/03/2002 | US6444536 Method for fabricating bipolar transistors |
| 09/03/2002 | US6444535 Method to reduce emitter to base capacitance and related structure |
| 09/03/2002 | US6444534 SOI semiconductor device opening implantation gettering method |
| 09/03/2002 | US6444533 Semiconductor devices and methods for same |