Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
09/2002
09/03/2002US6444532 Process for fabricating MOS semiconductor transistor
09/03/2002US6444531 Reverses order of source/drain and extension implants, avoids one block out masking process for each reduction in spacer thickness
09/03/2002US6444530 Process for fabricating an integrated circuit with a self-aligned contact
09/03/2002US6444529 Methods of forming integrated circuitry and methods of forming elevated source/drain regions of a field effect transistor
09/03/2002US6444528 Selective oxide deposition in the bottom of a trench
09/03/2002US6444527 Method of operation of punch-through field effect transistor
09/03/2002US6444526 Simplified process for defining the tunnel area in non-aligned, non-volatile semiconductor memory cells
09/03/2002US6444525 Vertical, has two trenches to minimize size
09/03/2002US6444524 Method for forming a trench capacitor
09/03/2002US6444523 Performing channel doping step on substrate so that actual threshold voltage of memory device is greater than preset threshold voltage, forming stack gate on substrate and source/drain region in substrate
09/03/2002US6444522 Forming photoresist pattern exposing portion of semiconductor substrate in which well region will be formed, doping to form well, removing pattern, forming second pattern, doping to form antidiffusion region and second well, thermally activating
09/03/2002US6444521 Replacing silicon nitride of nitride read only memory floating gate with silicon oxynitride improves endurance and reliability of device and extends data retention times
09/03/2002US6444520 Selectively removing protective layer of semiconductor substrate down to regions of each conductivity type and to protective cap of active device to provide openings that are subsequently filled with each type of conductive material
09/03/2002US6444519 Method for forming a capacitor in a mixed mode circuit device by ion implantation
09/03/2002US6444518 Method and manufacturing a device separation film in a semiconductor device
09/03/2002US6444517 Creating high q value spiral inductor by increasing metal thickness of inductor
09/03/2002US6444516 Semiconductor having gate structure employing gate conductor that has relatively low resistivity yet remains thermally stable at processing temperatures, thus exhibiting low gate propagation delay
09/03/2002US6444515 Forming on semiconductor substrate gate electrode, hard mask insulating layer, thin insulating layer, nitride stopper layer, sidewall nitride layer, interlayer insulating layer, and interconnection layer formed in contact hole in interlayer
09/03/2002US6444514 Semiconductor integrated circuit device and manufacturing method thereof
09/03/2002US6444513 Forming first metal layer on gate oxide on substrate, increasing etch selectivity in surface region of metal layer, forming second metal layer, etching to form metal gate, with etching stopping on surface region of first metal layer
09/03/2002US6444512 Dual metal gate transistors for CMOS process
09/03/2002US6444511 New cascaded nmos transistor output circuit with enhanced esd protection is achieved. a driver pmos transistor has the source connected to a voltage supply, the gate connected to the input signal, and the drain connected to the output pad.
09/03/2002US6444509 High performance poly-si1−xgex thin film transistor and a method of fabricating such a thin film transistor
09/03/2002US6444508 Method of manufacturing thin film transistor
09/03/2002US6444507 Fabrication process for thin film transistors in a display or electronic device
09/03/2002US6444506 It with a laser beam in a hydrogen-inclusive atmosphere. further, the above laser annealing step and a step of forming an insulating film to become a gate insulating film are performed consecutively. as a result, hydrogen is effectively
09/03/2002US6444505 Thin film transistor (TFT) structure with planarized gate electrode
09/03/2002US6444503 First patterned dielectric layer is formed over the substrate.
09/03/2002US6444501 Two stage transfer molding method to encapsulate MMC module
09/03/2002US6444500 Resin-encapsulating a substrate on which a plurality of semiconductor chips are formed, includes a first mold and a second mold. the second mold has a pressing surface that is provided with a mold release sheet.
09/03/2002US6444499 The snapable multi-package substrate is formed with trenches that separate and define sections where individual packaged electronic components are fabricated in a snapable multi-package array, and where individual packaged electronic
09/03/2002US6444498 Method of making semiconductor package with heat spreader
09/03/2002US6444497 Method and apparatus for reducing BGA warpage caused by encapsulation
09/03/2002US6444495 A colloidal suspension of nanoparticles composed of a dense material dispersed in a solvent is used in forming a gap-filling dielectric material with low thermal shrinkage. the dielectric material is particularly useful for pre-metal
09/03/2002US6444494 Separating individual film substrates from a film substrate tape having a plurality of said film substrates continuously and integrally connected to and second surfaces, a circuit pattern being formed on said first surface and a mounting
09/03/2002US6444493 Method for vertically integrating active circuit planes and vertically integrated circuit produced using said method
09/03/2002US6444492 Opening communicated with the hollow portion or fit in the opening of the plate support through an o-ring, suction holes penetrating through the mounting board holding surface to cover the suction holes and the suction means applying suction
09/03/2002US6444489 Semiconductor chip assembly with bumped molded substrate
09/03/2002US6444484 Fabricating a semiconductor device on a substrate comprising the steps of: forming a first conductive layer on the substrate; forming an insulation layer on the first conductive layer;and a second conductive layer with overlapping and
09/03/2002US6444483 A full area of a semiconductor integrated circuit is divided into unit areas, a mask data file for use in a beam exposure system or an inspection apparatus is produced based on cad data of the full area, full-area header information in which a
09/03/2002US6444482 Method of monitoring power supplied to heat a substrate
09/03/2002US6444481 Measuring a thickness of the process layer; and determining at least one plating parameter of the recipe for subsequently formed process layers based on the measured thickness. a processing line includes a plating tool, a metrology tool,
09/03/2002US6444480 Providing a semiconductor device fabrication apparatus comprising a thermal treatment device selected from the group consisting of a chemical vapor deposition sputtering device and a thermal diffusion device including an annealing furnace,
09/03/2002US6444479 Method for forming capacitor of semiconductor device
09/03/2002US6444478 Barium-strontium-titanate film, preferably having a thickness of less than about 600 .ang.. according to the present invention, the dielectric film is preferably formed using a chemical vapor deposition process in which an interfacial
09/03/2002US6444409 Scrubbing unit
09/03/2002US6444408 Polymerizable monomers having silicon containing groups that are transparent; and ethylenically unsaturated group are provided. and images
09/03/2002US6444406 Method for forming photoresist pattern and manufacturing method of magnetoresistive effect thin-film magnetic head
09/03/2002US6444405 Method of forming conductive layers in the trenches or through holes made in an insulating film on a semiconductors substrate
09/03/2002US6444404 Forming metal silicide blocking regions, using the same photolithographic mask for development. the process features the formation of an implanted esd region, defined by a photoresist shape which formed via exposure of a negative
09/03/2002US6444402 Method of fabricating a semiconductor device including steps of patterning a resist to form a first mask pattern, transferring said first mask pattern to an underlying layer of material, block-out masking a portion of said first mask
09/03/2002US6444399 Methods for achieving reduced effects of overlayer and subfield-stitching errors in charged-particle-beam microlithography, and device manufacturing methods comprising such microlithography methods
09/03/2002US6444398 Method for manufacturing a semiconductor wafer using a mask that has several regions with different scattering ability
09/03/2002US6444397 Amplification; photolithography patterning
09/03/2002US6444395 Pattern formation material and method
09/03/2002US6444394 Chemical-amplification positive-working photoresist composition capable of giving a patterned resist layer with excellent properties such as photosensitivity, pattern resolution, heat resistance and cross sectional profile of the
09/03/2002US6444390 Under the conditions in that a germanium film is formed on an amorphous silicon film, a first heat treatment (crystallization step) no defect in its crystal grain.
09/03/2002US6444375 Increasing integration of semiconductor devices via narrowing the width of the pattern formed in the mask pattern and the distance between; photolithography; semiconductors; integrated circuits
09/03/2002US6444374 Dividing the mask into partial areas, forming partial masks which have apertures with patterns identical with plurality of partial areas, exposing the patterns of masks on a mask substrate by electron beam proximity exposure method
09/03/2002US6444372 Non absorbing reticle and method of making same
09/03/2002US6444336 Thin film dielectric composite materials
09/03/2002US6444327 Silicon oxide film, method of forming the silicon oxide film, and apparatus for depositing the silicon oxide film
09/03/2002US6444310 Dicing tape and a method of dicing a semiconductor wafer
09/03/2002US6444296 Electrical resistance, electrodes
09/03/2002US6444277 Method for depositing amorphous silicon thin films onto large area glass substrates by chemical vapor deposition at high deposition rates
09/03/2002US6444265 Method for producing a titanium monophosphide layer and its use
09/03/2002US6444262 Substrate holder; interior vacuum; film forming semiconductor
09/03/2002US6444256 Formation of nanometer-size wires using infiltration into latent nuclear tracks
09/03/2002US6444255 Brush cleaning an electrode substrate with a hydrogen gas dissolved water of given oxidation-reduction potential and basic ph, before applying an alignment layer
09/03/2002US6444139 Chemical mechanical polishing
09/03/2002US6444138 Method of fabricating microelectromechanical and microfluidic devices
09/03/2002US6444137 Sputtering, ion etching, vapor deposition
09/03/2002US6444136 Fabrication of improved low-k dielectric structures
09/03/2002US6444110 Soluble copper salt, electrolyte, one or more brightener compounds that are present in a concentration of at least about 1.5 mg per liter of electroplating composition; increased brightener levels
09/03/2002US6444104 Sputtering target having an annular vault
09/03/2002US6444101 Contact ring for electroplating a substrate having an electroconductive portion, comprising an annular insulative body with central opening, a conductive biasing member coupled to the body to exert a biasing force on the substrate
09/03/2002US6444099 Ionizing sputtering method
09/03/2002US6444087 Cells having carbon or silicon carbide electrodes with dielectric quartz or silicon nitride coverings and gas generators used for vacuum deposition; noncontamination
09/03/2002US6444085 Plasma gases generators cells having semiconductors ceillings and side walls connected to power sources, supports and coils
09/03/2002US6444084 Low density high frequency process for a parallel-plate electrode plasma reactor having an inductive antenna
09/03/2002US6444082 Apparatus and method for removing a bonded lid from a substrate
09/03/2002US6444047 Method of cleaning a semiconductor substrate
09/03/2002US6444042 Restricts generation of contaminating particles by facilitating temperature control of shower head unit; even injection of gases onto wafers
09/03/2002US6444041 Methods, complexes, and system for forming metal-containing films
09/03/2002US6444040 Gas distribution plate
09/03/2002US6444039 Three-dimensional showerhead apparatus
09/03/2002US6444037 Can provide high temperature deposition, heating and efficient cleaning, for forming dielectric films having thickness uniformity, good gap fill capability, high density and low moisture
09/03/2002US6444036 Construction of a film on a semiconductor wafer
09/03/2002US6444035 Conveyorized vacuum injection system
09/03/2002US6444034 Apparatus for eliminating electrostatic destruction
09/03/2002US6444029 Compact photolithography device for developing photoresist on semiconductor wafer; vertically stacked compartments; enhanced throughput
09/03/2002US6444027 Improved quality semiconductor wafers; complete cleaning and removal of native oxide from back surface; reduced autodoping of front surface; eliminating halo affect; preventing wafer float during loading
09/03/2002US6444010 Aqueous solution of hydrogen peroxide, hydrogen fluoride and high concentration of hydrochloric acid or sulfuric acid; dissolving palladium, iridium, osmium, ruthenium and rhenium for removal from silicon surface or silicon oxide film
09/03/2002US6443826 Polishing head of a chemical mechanical polishing apparatus and, retainer ring of the same
09/03/2002US6443824 Fluid-pressure regulated wafer polishing head
09/03/2002US6443821 Workpiece carrier and polishing apparatus having workpiece carrier
09/03/2002US6443820 Polishing apparatus
09/03/2002US6443816 Method and apparatus for cleaning polishing surface of polisher
09/03/2002US6443814 Method and chemistry for cleaning of oxidized copper during chemical mechanical polishing
09/03/2002US6443812 Chemical mechanical polishing (cmp) with pad made of such as polyvinylpyrrolidone having affinity for surface groups on a semiconductor wafer; nonscratching, smoothness, noncoating