Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
09/2002
09/10/2002US6448537 Single-wafer process chamber thermal convection processes
09/10/2002US6448536 Single-substrate-heat-processing apparatus for semiconductor process
09/10/2002US6448533 Method of repairing disconnected wiring and multilevel wiring structure
09/10/2002US6448510 Substrate for electronic packaging, pin jig fixture
09/10/2002US6448509 Printed circuit board with heat spreader and method of making
09/10/2002US6448507 Solder mask for controlling resin bleed
09/10/2002US6448383 Method for producing 1,2-naphthoquinonediazide photosensitive agent
09/10/2002US6448331 Such as tetraethoxysilane, polyethylene glycol, amide or ester solvent and acid catalyst that promotes hydrolysis and dehydration condensation; low dielectric constant layers for multilevel interconnects; produced by current techniques
09/10/2002US6448192 Method for forming a high dielectric constant material
09/10/2002US6448191 Dissolving barium, strontium, and titanium dipivaloyl compounds in an organic solvent, vaporizing, depositing to form barium strontium titanium oxide coating
09/10/2002US6448190 Method and apparatus for fabrication of integrated circuit by selective deposition of precursor liquid
09/10/2002US6448189 Method of manufacturing a semiconductor memory device having a capacitor with improved dielectric layer
09/10/2002US6448188 Method of preventing motion of article in an article holder
09/10/2002US6448187 Depositing a silicon oxide film by oxidation of silicon compound, exposing to water or a hydrophobic-imparting surfactant such as hexamethyldisilazane and curing
09/10/2002US6448186 Method and apparatus for use of hydrogen and silanes in plasma
09/10/2002US6448185 A first etched region (e.g., a via or trench) is filled with a sacrificial light absorbing material that may comprise a dyed spin-on-glass with light absorbing properties that enable the substrate to absorb light during lithography
09/10/2002US6448184 Formation of diamond particle interconnects
09/10/2002US6448183 Method of forming contact portion of semiconductor element
09/10/2002US6448182 Stabilization of peroxygen-containing slurries used in a chemical mechanical planarization
09/10/2002US6448181 Introducing only one of a high melting metal composition gas and a reducing gas for a short time as a pre-process just before the film forming process to improve repeatability of a thickness and uniformity of thickness of the film
09/10/2002US6448180 Deposition of in-situ doped semiconductor film and undoped semiconductor film in the same reaction chamber
09/10/2002US6448179 Forming large contact plug
09/10/2002US6448178 Heating in an oxidizing atmosphere prevents dopants such as the phosphorous atoms from escaping from the thin film and increasing the resistance of the film
09/10/2002US6448177 Method of making a semiconductor device having a dual damascene interconnect spaced from a support structure
09/10/2002US6448176 Dual damascene processing for semiconductor chip interconnects
09/10/2002US6448175 Method for forming insulating thin films
09/10/2002US6448174 Wiring method for producing a vertical, integrated circuit structure and vertical, integrated circuit structure
09/10/2002US6448173 Aluminum-based metallization exhibiting reduced electromigration and method therefor
09/10/2002US6448172 Manufacturing method of forming interconnection in semiconductor device
09/10/2002US6448171 Microelectronic fabrication having formed therein terminal electrode structure providing enhanced passivation and enhanced bondability
09/10/2002US6448170 Method of producing external connector for substrate
09/10/2002US6448167 Process flow to reduce spacer undercut phenomena
09/10/2002US6448166 Forming one of a silicon oxide and a sillicon oxynitride film on semiconductor substrate, covering it with amorphous tantalum oxynitride layer, performing low temperature annealing, crystallizing the amorphous tantalum oxynitride
09/10/2002US6448165 Method for controlling the amount of trim of a gate structure of a field effect transistor
09/10/2002US6448164 Dark field image reversal for gate or line patterning
09/10/2002US6448163 Method for fabricating T-shaped transistor gate
09/10/2002US6448162 Method for producing schottky diodes
09/10/2002US6448161 Silicon based vertical tunneling memory cell
09/10/2002US6448160 Method of fabricating power rectifier device to vary operating parameters and resulting device
09/10/2002US6448159 Chemical mechanical polishing for forming a shallow trench isolation structure
09/10/2002US6448157 Fabrication process for a semiconductor device
09/10/2002US6448156 Techniques for maintaining alignment of cut dies during substrate dicing
09/10/2002US6448155 Production method of semiconductor base material and production method of solar cell
09/10/2002US6448154 Method for producing wafers with rounded corners in the notches used for alignment in the fabrication of semiconductor devices
09/10/2002US6448153 Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners
09/10/2002US6448152 Method and system for generating a plurality of donor wafers and handle wafers prior to an order being placed by a customer
09/10/2002US6448151 Process for producing a large number of semiconductor chips from a semiconductor wafer
09/10/2002US6448150 Method for forming shallow trench isolation in the integrated circuit
09/10/2002US6448149 Deposition of capping oxide layer after filling trenches with high density plasma-chemical vapor deposition oxide layer results in improvement in the leakage current and refresh characteristics of the transistors
09/10/2002US6448148 Method for forming a thin film
09/10/2002US6448147 Semiconductor device and method for manufacturing the same
09/10/2002US6448146 The electrodes are formed on an inner surface of the exposed lower capacitor electrode, reducing the likelihood of lower electrode breakage and shorting (e.g., stringer formation) during fabrication. electrode.
09/10/2002US6448145 Capacitor for semiconductor device and method for manufacturing the same
09/10/2002US6448143 Method for using thin spacers and oxidation in gate oxides
09/10/2002US6448142 Method for fabricating a metal oxide semiconductor transistor
09/10/2002US6448141 Graded LDD implant process for sub-half-micron MOS devices
09/10/2002US6448140 Laterally recessed tungsten silicide gate structure used with a self-aligned contact structure including a straight walled sidewall spacer while filling recess
09/10/2002US6448139 Manufacturing method of semiconductor device
09/10/2002US6448138 Nonvolatile floating-gate memory devices, and process of fabrication
09/10/2002US6448137 Method of forming an NROM embedded with mixed-signal circuits
09/10/2002US6448136 Method of manufacturing flash memory
09/10/2002US6448135 Semiconductor device and method of fabricating same
09/10/2002US6448134 Method for fabricating semiconductor device
09/10/2002US6448133 Method to form a DRAM capacitor using low temperature reoxidation
09/10/2002US6448132 Semiconductor device having a lower electrode aperture that is larger than the photolithography resolution of the capacitor pattern
09/10/2002US6448131 Method for increasing the capacitance of a trench capacitor
09/10/2002US6448130 Method of selectively forming silicide film of merged DRAM and Logic
09/10/2002US6448129 Applying epitaxial silicon in disposable spacer flow
09/10/2002US6448128 Capacitor for semiconductor memory device and method of manufacturing the same
09/10/2002US6448127 Deep submicron complementary metal oxide semiconductor (cmos) integrated circuit; removing initial oxide layer on silicon wafer by hydrogen baking; forming new oxide or oxynitride layer; removing a portion oxide layer by hydrogen annealing
09/10/2002US6448126 Method of forming an embedded memory
09/10/2002US6448125 Electronic power device integrated on a semiconductor material and related manufacturing process
09/10/2002US6448124 Method for epitaxial bipolar BiCMOS
09/10/2002US6448122 Method and device structure for enhanced ESD performance
09/10/2002US6448121 High threshold PMOS transistor in a surface-channel process
09/10/2002US6448120 Totally self-aligned transistor with tungsten gate
09/10/2002US6448119 Field effect transistor and method of fabricating the same
09/10/2002US6448118 Semiconductor film manufacturing with selective introduction of crystallization promoting material
09/10/2002US6448117 Tri-layer process for forming TFT matrix of LCD with gate metal layer around pixel electrode as black matrix
09/10/2002US6448115 Semiconductor device having quasi-SOI structure and manufacturing method thereof
09/10/2002US6448114 Method of fabricating a silicon-on-insulator (SOI) chip having an active layer of non-uniform thickness
09/10/2002US6448113 Method of forming fuse area structure including protection film on sidewall of fuse opening in semiconductor device
09/10/2002US6448112 Cell array region of a NOR-type mask ROM device and fabricating method therefor
09/10/2002US6448111 Method of manufacturing a semiconductor device
09/10/2002US6448109 Wafer level method of capping multiple MEMS elements
09/10/2002US6448108 Method of making a semiconductor chip assembly with a conductive trace subtractively formed before and after chip attachment
09/10/2002US6448106 Modules with pins and methods for making modules with pins
09/10/2002US6448105 Method for doping one side of a semiconductor body
09/10/2002US6448104 CMOS type solid imaging device
09/10/2002US6448103 Method for making an accurate miniature semiconductor resonator
09/10/2002US6448102 Method for nitride based laser diode with growth substrate removed
09/10/2002US6448101 Method of integrating a photodiode and a CMOS transistor with a non-volatile memory
09/10/2002US6448100 Method for fabricating self-aligned field emitter tips
09/10/2002US6448097 Measure fluorescence from chemical released during trim etch
09/10/2002US6448095 Circuit access and analysis for a SOI flip-chip die
09/10/2002US6448094 Method of detecting etching depth
09/10/2002US6447980 Photoresist composition for deep UV and process thereof
09/10/2002US6447975 Produces a photoresist layer, photosensitive chemical, and solvents without unpleasant odor
09/10/2002US6447960 Electron beam exposure mask and pattern designing method thereof
09/10/2002US6447933 Formation of alloy material using alternating depositions of alloy doping element and bulk material
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