Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
12/2002
12/10/2002US6491202 Wire bonding apparatus and method
12/10/2002US6491178 Upper cover plate for an air-tight chamber and a tool for removing the same
12/10/2002US6491177 Thin-plate accommodating/transporting container
12/10/2002US6491083 Wafer demount receptacle for separation of thinned wafer from mounting carrier
12/10/2002US6491046 Vertical batch type wafer cleaning apparatus
12/10/2002US6491045 Apparatus for and method of cleaning object to be processed
12/10/2002US6491043 Ultra-low particle semiconductor cleaner
12/10/2002US6491042 Post etching treatment process for high density oxide etcher
12/10/2002US6490994 Plasma processing apparatus
12/10/2002US6490810 Vacuum processing apparatus
12/10/2002CA2256601C Method for testing electronic components
12/10/2002CA2146680C Cleaning wafer substrates of metal contamination while maintaining wafer smoothness
12/09/2002CA2448006A1 High voltage, high temperature capacitor structures and methods of fabricating same
12/05/2002WO2002098175A2 Device for heating substrates with side screens and/or secondary reflectors
12/05/2002WO2002098125A1 Signal processing circuit and solid-state image pickup device
12/05/2002WO2002097963A2 Dielectric resonator
12/05/2002WO2002097899A2 Integrated tunable capacitor
12/05/2002WO2002097898A1 High q varactor diodes
12/05/2002WO2002097896A1 Process for making a high voltage npn bipolar device with improved ac performance
12/05/2002WO2002097895A2 Transistor, method for producing an integrated circuit and method for producing a metal silicide layer
12/05/2002WO2002097893A1 Method of manufacturing laminated wafer
12/05/2002WO2002097892A1 Soi substrate
12/05/2002WO2002097891A2 Dram cell arrangement with vertical mos transistors and method for the production thereof
12/05/2002WO2002097890A2 Bitline contacts in a memory cell array
12/05/2002WO2002097889A2 Semiconductor device and a method therefor
12/05/2002WO2002097888A1 Power semiconductor device
12/05/2002WO2002097887A1 Substrate noise isolation using selective buried diffusions
12/05/2002WO2002097881A2 Folded-fin heat sink assembly and method of manufacturing same
12/05/2002WO2002097879A1 Precision substrate storage container and retaining member therefor
12/05/2002WO2002097878A2 Method and apparatus for determining process layer conformality
12/05/2002WO2002097877A1 A method of packaging a semiconductor chip
12/05/2002WO2002097876A2 Manufacture of trench-gate field-effect transistors
12/05/2002WO2002097875A1 Method for preparing nitrogen-doped and annealed wafer and nitrogen-doped and annealed wafer
12/05/2002WO2002097874A1 Method for deep and vertical dry etching of dielectrics
12/05/2002WO2002097873A1 Masking technique for producing semiconductor components, in particular a buried heterostructure (bh) laser diode
12/05/2002WO2002097872A1 Method of fabricating semiconductor wafer and susceptor used therefor
12/05/2002WO2002097871A2 Structure and method for fabricating semiconductor devices
12/05/2002WO2002097870A2 Diffuser and rapid cycle chamber
12/05/2002WO2002097869A2 Method and apparatus to correct wafer drift
12/05/2002WO2002097868A2 Integrated circuit having an energy-absorbing structure
12/05/2002WO2002097867A1 Arrangement comprising a support body with a substrate holder mounted thereon on a gas bearing with rotating drive
12/05/2002WO2002097866A2 Method of etching dielectric materials
12/05/2002WO2002097864A2 Low temperature load and bake
12/05/2002WO2002097863A2 Method for manufacturing contacts for a chalcogenide memory device
12/05/2002WO2002097861A2 Semiconductor device, semiconductor layer and production method thereof
12/05/2002WO2002097855A1 Plasma processing apparatus and method
12/05/2002WO2002097853A1 Methods and apparatus for ion implantation with variable spatial frequency scan lines
12/05/2002WO2002097852A2 Plasma etching of silicon carbide
12/05/2002WO2002097820A2 Pair wise programming method for dual cell eeprom
12/05/2002WO2002097508A1 Optical system and exposure system provided with the optical system
12/05/2002WO2002097453A1 Probe card, probe, probe manufacturing method, and probe card manufacturing method
12/05/2002WO2002097452A1 Method for manufacture of probe pin, and method for manufacture of probe card
12/05/2002WO2002097366A1 Observation device using light and x-ray, exposure system and exposure method
12/05/2002WO2002097363A1 Position detection apparatus, position detection method, electronic part carrying apparatus, and electronic beam exposure apparatus
12/05/2002WO2002097326A1 Antistatic optical pellicle
12/05/2002WO2002097173A2 Semi-insulating silicon carbide without vanadium domination
12/05/2002WO2002097172A2 Molecular beam epitaxy equipment
12/05/2002WO2002097165A2 Apparatus and methods for electrochemical processing of microelectronic workpieces
12/05/2002WO2002097158A1 Application of dense plasmas generated at atmospheric pressure for treating gas effluents
12/05/2002WO2002097154A1 Plasma treatment container internal member, and plasma treatment device having the plasma treatment container internal member
12/05/2002WO2002097145A1 Compositions, methods and devices for high temperature lead-free solder
12/05/2002WO2002096999A1 Cerium oxide slurry, and method of manufacturing substrate
12/05/2002WO2002096799A2 Silicon subnitride method for production and use of said subnitride
12/05/2002WO2002096632A2 Dual-cell soft programming for virtual-ground memory arrays
12/05/2002WO2002096612A1 Substrate and method of separating components from a substrate
12/05/2002WO2002096601A1 Polishing apparatus and polishing method
12/05/2002WO2002089192A8 Method of wet etching an inorganic antireflection layer
12/05/2002WO2002080219B1 Stacked rf excitation coil for inductive plasma processor
12/05/2002WO2002069408A3 Soi ldmos transistor having a field plate and method of making the same
12/05/2002WO2002067314A3 High temperature short time curing of low dielectric constant materials using rapid thermal processing techniques
12/05/2002WO2002063669A3 Method and apparatus for two-step barrier layer polishing
12/05/2002WO2002056365A3 Method for subdividing wafers into chips
12/05/2002WO2002054456A3 A rinsing solution and rinsing and drying methods for the prevention of watermark formation on a surface
12/05/2002WO2002050914A3 A semiconductor device with bias contact
12/05/2002WO2002050894A3 Structural reinforcement of highly porous low k dielectric films by cu diffusion barrier structures
12/05/2002WO2002049114A3 High withstand voltage semiconductor device
12/05/2002WO2002047158A3 Ionized metal plasma deposition process having enhanced via sidewall coverage
12/05/2002WO2002043067A3 Integrated memory with an arrangement of non-volatile memory cells and method for the production and operation of an integrated memory
12/05/2002WO2002041403A3 Mos low-voltage vertical transistor
12/05/2002WO2002037569A9 Trench gate mos semiconductor device
12/05/2002WO2002027060A3 Process chamber lid service system
12/05/2002WO2001050498A9 Linear drive system for use in a plasma processing system
12/05/2002US20020184606 LSI design method having dummy pattern generation process and LCR extraction process and computer program therefor
12/05/2002US20020184605 Method and apparatus of evaluating layer matching deviation based on CAD information
12/05/2002US20020184604 Coordinate transformation system for semiconductor device, coordinate transformation method and coordinate transformation program
12/05/2002US20020184602 Database for designing integrated circuit device, and method for designing integrated circuit device
12/05/2002US20020184587 Apparatus and method for test-stimuli compaction
12/05/2002US20020184584 Scan flip-flop circuit, logic macro, scan test circuit, and method for laying out the same
12/05/2002US20020184583 Cell having scan functions and a test circuit of a semiconductor integrated circuit
12/05/2002US20020184558 Substrate noise isolation using selective buried diffusions
12/05/2002US20020183991 Method for modeling semiconductor device process
12/05/2002US20020183989 Overlay error model, sampling strategy and associated equipment for implementation
12/05/2002US20020183977 Endpoint detection in substrate fabrication processes
12/05/2002US20020183949 System for dynamically monitoring the stability of semiconductor manufacturing equipment
12/05/2002US20020183885 Multi-computer chamber control system, method and medium
12/05/2002US20020183884 Method for continuous, non lot-based integrated circuit manufacturing
12/05/2002US20020183880 Remote maintenance method, industrial device, and semiconductor device
12/05/2002US20020183879 Method for controlling a process appliance for the sequential processing of semiconductor wafers
12/05/2002US20020183876 Remote maintenance method, industrial device, and semiconductor device
12/05/2002US20020183875 Remote maintenance method, industrial device, and semiconductor device
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