Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
12/2002
12/05/2002US20020183476 Using aromatic aliphatic ether solvents, such as anisole, methylanisole, and phenetole, as clean-up solvent or as part of a coating solution for polymeric dielectric materials; microelectronics
12/05/2002US20020183426 Crosslinkable fill compositions for uniformly protecting via and contact holes
12/05/2002US20020183219 Used for removing photoresist or other residue from a substrate, such as an integrated circuit
12/05/2002US20020182996 Methods for carrier head with multi-part flexible membrane
12/05/2002US20020182995 Chemical mechanical polishing carrier head
12/05/2002US20020182985 Polishing method for removing corner material from a semi-conductor wafer
12/05/2002US20020182968 Method of manufacturing an electro-optical device
12/05/2002US20020182894 Method of making a semiconductor device using a silicon carbide hard mask
12/05/2002US20020182893 Oxidation of silicon nitride films in semiconductor devices
12/05/2002US20020182892 Wafer transfer method performed with vapor thin film growth system and wafer support member used for this method
12/05/2002US20020182891 Method of forming dielectric film and dielectric film
12/05/2002US20020182889 Free standing substrates by laser-induced decoherency and regrowth
12/05/2002US20020182888 Apparatus and method for forming an oxynitride insulating layer on a semiconductor wafer
12/05/2002US20020182887 Method and apparatus of forming a sputtered doped seed layer
12/05/2002US20020182886 plastic films used for hermetic sealing OLED; sandwiching the organic films between inorganic films, stress can be relaxed, and even if one of the inorganic films has a crack, the other inorganic films can prevent oxygen or water from penetrating the OLED; relaxed stress results in reduced cracking
12/05/2002US20020182884 Apparatus and method for manufacturing a semiconductor circuit
12/05/2002US20020182882 Method for reducing contamination prior to epitaxial growth and related structure
12/05/2002US20020182881 Method of plasma etching organic antireflective coating
12/05/2002US20020182880 Method of plasma etching silicon nitride
12/05/2002US20020182879 Masking method for producing semiconductor components, particularly a BH laser diode
12/05/2002US20020182878 Pressure control method
12/05/2002US20020182876 Semiconductor device fabrication method and apparatus
12/05/2002US20020182875 Method of manufacturing a mono-crystalline silicon ball
12/05/2002US20020182874 Method for forming hybrid low-k film stack to avoid thermal stress effect
12/05/2002US20020182873 In-situ mask technique for producing III-V semiconductor components
12/05/2002US20020182872 Material removal method for forming a structure
12/05/2002US20020182871 Coating a polysilane on a semiconductor substrate and coating a resist on polysilane; patterning resist with exposure and development; transferring pattern from resist to polysilane by etching; thermal/plasma oxidation to form silica; etching
12/05/2002US20020182870 Substrate processing apparatus and a method for fabricating a semiconductor device by using same
12/05/2002US20020182869 Method for forming dual-damascene interconnect structure
12/05/2002US20020182865 Plasma processing apparatus and method for forming thin films using the same
12/05/2002US20020182864 Etching process
12/05/2002US20020182862 Optimized TaCN thin film diffusion barrier for copper metallization
12/05/2002US20020182860 Method of forming self-aligned silicide layers on semiconductor devices
12/05/2002US20020182859 Structures and methods to enhance copper metallization
12/05/2002US20020182858 Forming insulator layer having substance, forming inhibiting layer on insulator layer, wherein forming inhibiting layer includes depositing second substance on insulator layer, forming a copper metallization layer on the inhibiting layer
12/05/2002US20020182857 Damascene process in intergrated circuit fabrication
12/05/2002US20020182856 Method for forming a contact window with low resistance
12/05/2002US20020182855 Dual damascene multi-level metallization
12/05/2002US20020182854 Method of manufacturing a semiconductor device with a contact hole
12/05/2002US20020182853 Method for removing hard-mask layer after metal-CMP in dual-damascene interconnect structure
12/05/2002US20020182852 Method for reducing micro-masking defects in trench isolation regions
12/05/2002US20020182851 Process for preparing cu damascene interconnection
12/05/2002US20020182850 Interconnect structure manufacturing process
12/05/2002US20020182849 Method for fabricating a low dielectric constant material layer
12/05/2002US20020182848 Method of improving the fabrication of etched semiconductor devices
12/05/2002US20020182847 Method of manufacturing semiconductor device
12/05/2002US20020182846 Semiconductor devices having contact plugs and local interconnects and methods for making the same
12/05/2002US20020182845 Method of filling a concave portion with an insulating material
12/05/2002US20020182844 Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method
12/05/2002US20020182843 Method for connecting semiconductor unit to object via bump
12/05/2002US20020182841 Compliant integrated circuit package
12/05/2002US20020182840 Method for the sulphidation treatment of III-V compound semiconductor surfaces
12/05/2002US20020182839 Method for fabricating group III nitride semiconductor substrate
12/05/2002US20020182838 Fuse in semiconductor device and fabricating method thereof
12/05/2002US20020182836 Forming an alloy layer over a silicon-containing substrate, annealing alloy layer to form a metal alloy silicide, removing any remaining alloy layer
12/05/2002US20020182835 Method for manufacturing contacts for a Chalcogenide memory device
12/05/2002US20020182834 Method of manufacturing a transistor with a footed offset spacer
12/05/2002US20020182833 Method of manufacturing an array substrate having drive integrated circuits
12/05/2002US20020182832 Method and article for filling apertures in a high performance electronic substrate
12/05/2002US20020182831 Semiconductor device and method of manufacturing the same
12/05/2002US20020182830 Method of forming a resist pattern for blocking implantation of an impurity into a semiconductor substrate
12/05/2002US20020182829 Method for forming nitride read only memory with indium pocket region
12/05/2002US20020182828 Semiconductor film, semiconductor device and method of their production
12/05/2002US20020182827 Semiconductor wafer and method for producing the same
12/05/2002US20020182826 Fabrication method for a shallow trench isolation structure
12/05/2002US20020182825 Method for improving thickness uniformity of deposited ozone-TEOS silicate glass layers
12/05/2002US20020182824 Method of forming shallow trench isolation
12/05/2002US20020182822 Structure and method for MOSFET with metallic gate electrode
12/05/2002US20020182821 Method of manufacturing an alignment mark
12/05/2002US20020182820 Method of forming a capacitor of an integrated circuit device
12/05/2002US20020182819 Method for fabricating an insulation collar in a trench capacitor
12/05/2002US20020182818 Thin film devices and method for fabricating thin film devices
12/05/2002US20020182817 Resist mask for measuring the accuracy of overlaid layers
12/05/2002US20020182816 Material removal method for forming a structure
12/05/2002US20020182815 Novel self aligned channel implant, elevated S/D process by gate electrode damascene
12/05/2002US20020182814 Novel self aligned channel implant, elevated S/D process by gate electrode damascene
12/05/2002US20020182813 Graded LDD implant process for sub-half-micron MOS devices
12/05/2002US20020182812 Transistor structures, methods of incorporating nitrogen into silicon-oxide-containing layers; and methods of forming transistors
12/05/2002US20020182811 Novel masked nitrogen enhanced gate oxide
12/05/2002US20020182810 High power semiconductor device and fabrication method thereof
12/05/2002US20020182809 Method of fabricating an array of non-volatile memory cells
12/05/2002US20020182808 Method for fabricating an integrated circuit
12/05/2002US20020182807 Semiconductor device and method of manufacturing same
12/05/2002US20020182806 Nonvolatile memory device having STI structure and method of fabricating the same
12/05/2002US20020182805 Structure of a low-voltage channel write/erase flash memory cell and fabricating method thereof
12/05/2002US20020182804 Capacitor sheet, method for producing the same, board with built-in capacitors, and semiconductor device
12/05/2002US20020182803 Semiconductor devices having contact plugs and local interconnects and methods for making the same
12/05/2002US20020182802 Capacitor and method for fabricating the same
12/05/2002US20020182801 Semiconductor device and method for manufacturing the same
12/05/2002US20020182799 Method for manufacturing transistor
12/05/2002US20020182798 Semiconductor integrated circuit device, and method of manufacturing the same
12/05/2002US20020182797 Memory array with salicide isolation
12/05/2002US20020182796 Semiconductor device and manufacturing method thereof including a probe test step and a burn-in test step
12/05/2002US20020182795 Semiconductor transistor using L-shaped spacer and method of fabricating the same
12/05/2002US20020182794 Method of making stacked MIMCap between Cu dual-damascene levels
12/05/2002US20020182793 Transistors having selectively doped channel regions
12/05/2002US20020182790 Semiconductor fabrication apparatus having FOUP index in apparatus installation area
12/05/2002US20020182789 Thin film transistor and a method of forming the same
12/05/2002US20020182788 Photodiode CMOS imager with column-feedback soft-reset for imaging under ultra-low illumination and with high dynamic range
12/05/2002US20020182787 Semiconductor device having quasi-SOI structure and manufacturing method thereof
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