H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
12/2002
12/17/2002	US6495889 Semiconductor device having self-aligned contacts
12/17/2002	US6495888 Semiconductor device with p-n junction diode and method of forming the same
12/17/2002	US6495887 Argon implantation after silicidation for improved floating-body effects
12/17/2002	US6495886 Semiconductor thin film and semiconductor device
12/17/2002	US6495885 Graded LDD implant process for sub-half-micron MOS devices
12/17/2002	US6495882 Short-channel schottky-barrier MOSFET device
12/17/2002	US6495881 Programmable read only memory in CMOS process flow
12/17/2002	US6495880 Method to fabricate a flash memory cell with a planar stacked gate
12/17/2002	US6495879 Ferroelectric memory device having a protective layer
12/17/2002	US6495878 Interlayer oxide containing thin films for high dielectric constant application
12/17/2002	US6495877 Metal capacitors with damascene structures and method for forming the same
12/17/2002	US6495876 DRAM strap: hydrogen annealing for improved strap resistance in high density trench DRAMS
12/17/2002	US6495875 Method of forming metal oxide metal capacitors using multi-step rapid material thermal process and a device formed thereby
12/17/2002	US6495874 Semiconductor device and production process thereof
12/17/2002	US6495873 Magnetoresistive element and use thereof as a memory element in a memory cell configuration
12/17/2002	US6495872 Ferroelectric capacitor and a method for manufacturing thereof
12/17/2002	US6495871 Power semiconductor element capable of improving short circuit withstand capability while maintaining low on-voltage and method of fabricating the same
12/17/2002	US6495870 Semiconductor device and method for patterning the semiconductor device in which line patterns terminate at different lengths to prevent the occurrence of a short or break
12/17/2002	US6495869 Method of manufacturing a double-heterojunction bipolar transistor on III-V material
12/17/2002	US6495868 Relaxed InxGa1−xAs buffers
12/17/2002	US6495867 InGaN/AlGaN/GaN multilayer buffer for growth of GaN on sapphire
12/17/2002	US6495866 Semiconductor device for preventing an increased clamp voltage in an ignition circuit
12/17/2002	US6495864 High-voltage semiconductor component, method for the production and use thereof
12/17/2002	US6495863 Semiconductor device having diode for input protection circuit of MOS structure device
12/17/2002	US6495860 Light emitting diode and manufacturing process thereof with blank
12/17/2002	US6495857 Thin film transister semiconductor devices
12/17/2002	US6495856 Semiconductor device having a test pattern same as conductive pattern to be tested and method for testing semiconductor device for short-circuit
12/17/2002	US6495855 Semiconductor device
12/17/2002	US6495853 Self-aligned gate semiconductor
12/17/2002	US6495841 Charged beam drawing apparatus
12/17/2002	US6495840 Ion-implanting method and ion-implanting apparatus
12/17/2002	US6495839 Microlithography projection objective and projection exposure apparatus
12/17/2002	US6495807 Heat treating method and heat treating apparatus
12/17/2002	US6495805 Method of determining set temperature trajectory for heat treatment system
12/17/2002	US6495802 Temperature-controlled chuck and method for controlling the temperature of a substantially flat object
12/17/2002	US6495800 Continuous-conduction wafer bump reflow system
12/17/2002	US6495791 Method and subsystem for generating a trajectory to be followed by a motor-driven stage when processing microstructures at a laser-processing site
12/17/2002	US6495773 Wire bonded device with ball-shaped bonds
12/17/2002	US6495769 Wiring board and production method thereof, and semiconductor apparatus
12/17/2002	US6495709 Nonaqueous organic precursor for forming aluminum oxide in solution
12/17/2002	US6495479 Coating with such as tetraacetoxysilane and a porogen, aging or condensing in presence of water and heating the gelled film
12/17/2002	US6495478 Reduction of shrinkage of poly(arylene ether) for low-K IMD
12/17/2002	US6495477 Method for forming a nitridized interface on a semiconductor substrate
12/17/2002	US6495476 Method for preventing native oxide growth during nitridation
12/17/2002	US6495475 Method for fabrication of a high capacitance interpoly dielectric
12/17/2002	US6495474 Method of fabricating a dielectric layer
12/17/2002	US6495473 Substrate processing apparatus and method of manufacturing semiconductor device
12/17/2002	US6495472 Method for avoiding erosion of conductor structure during removing etching residues
12/17/2002	US6495471 Etching process using a buffer layer
12/17/2002	US6495470 Contact and via fabrication technologies
12/17/2002	US6495469 High selectivity, low etch depth micro-loading process for non stop layer damascene etch
12/17/2002	US6495468 Laser ablative removal of photoresist
12/17/2002	US6495467 Method of fabricating a non-volatile memory device
12/17/2002	US6495466 Method of manufacturing a semiconductor device and a semiconductor device
12/17/2002	US6495465 Method for appraising the condition of a semiconductor polishing cloth
12/17/2002	US6495464 Method and apparatus for fixed abrasive substrate preparation and use in a cluster CMP tool
12/17/2002	US6495463 Method for chemical mechanical polishing
12/17/2002	US6495461 Process for forming amorphous titanium silicon nitride on substrate
12/17/2002	US6495460 Dual layer silicide formation using a titanium barrier to reduce surface roughness at silicide/junction interface
12/17/2002	US6495459 Metal precursor comprises a metal coordinated with at least one Lewis base to form a complex, and also a stoichiometric excess of Lewis base, such as carbon monoxide or ammonia
12/17/2002	US6495458 Method for producing low carbon/oxygen conductive layers
12/17/2002	US6495457 Method of reducing carbon incorporation into films produced by chemical vapor deposition involving organic precursor compounds
12/17/2002	US6495455 Method for enhancing selectivity between a film of a light-sensitive material and a layer to be etched in electronic semiconductor device fabrication processes
12/17/2002	US6495454 Substrate interconnect for power distribution on integrated circuits
12/17/2002	US6495453 Method for improving the quality of a metal layer deposited from a plating bath
12/17/2002	US6495452 Method to reduce capacitance for copper interconnect structures
12/17/2002	US6495451 Method of forming interconnect
12/17/2002	US6495450 Isolation using an antireflective coating
12/17/2002	US6495449 Multilayered diffusion barrier structure for improving adhesion property
12/17/2002	US6495448 Dual damascene process
12/17/2002	US6495447 Use of hydrogen doping for protection of low-k dielectric layers
12/17/2002	US6495446 Lossless microstrip line in CMOS process
12/17/2002	US6495445 Semi-sacrificial diamond for air dielectric formation
12/17/2002	US6495443 Method of re-working copper damascene wafers
12/17/2002	US6495442 Post passivation interconnection schemes on top of the IC chips
12/17/2002	US6495441 Semiconductor device with gold bumps, and method and apparatus of producing the same
12/17/2002	US6495440 Method to prevent an ITO from opening
12/17/2002	US6495439 Method for suppressing pattern distortion associated with BPSG reflow and integrated circuit chip formed thereby
12/17/2002	US6495438 Titanium polycide gate electrode and method of forming a titanium polycide gate electrode of a semiconductor device
12/17/2002	US6495437 Low temperature process to locally form high-k gate dielectrics
12/17/2002	US6495436 Formation of metal oxide gate dielectric
12/17/2002	US6495435 Method for improved control of lines adjacent to a select gate using a mask assist feature
12/17/2002	US6495433 Method of activating compound semiconductor layer to p-type compound semiconductor layer
12/17/2002	US6495432 Method of improving a dual gate CMOS transistor to resist the boron-penetrating effect
12/17/2002	US6495431 Semiconductor device and method for manufacturing the same that includes a dual oxidation
12/17/2002	US6495430 Process for fabricating sharp corner-free shallow trench isolation structure
12/17/2002	US6495429 Controlling internal thermal oxidation and eliminating deep divots in SIMOX by chlorine-based annealing
12/17/2002	US6495428 Method of making a capacitor with oxygenated metal electrodes and high dielectric constant materials
12/17/2002	US6495427 Method for forming a capacitor compatible with high dielectric constant materials having two independent insulative layers
12/17/2002	US6495426 Method for simultaneous formation of integrated capacitor and fuse
12/17/2002	US6495425 Memory cell structure integrating self aligned contact structure with salicide gate electrode structure
12/17/2002	US6495424 Semiconductor device
12/17/2002	US6495423 Electronic power device monolithically integrated on a semiconductor and comprising edge protection structures having a limited planar dimension
12/17/2002	US6495422 Methods of forming high-k gate dielectrics and I/O gate oxides for advanced logic application
12/17/2002	US6495421 Manufacture of semiconductor material and devices using that material
12/17/2002	US6495420 Method of making a single transistor non-volatile memory device
12/17/2002	US6495419 Nonvolatile memory in CMOS process flow
12/17/2002	US6495418 Method of manufacturing a semiconductor device having a capacitor
12/17/2002	US6495417 Method for increasing tolerance of contact extension alignment in COB DRAM
12/17/2002	US6495416 Semiconductor integrated circuit device with MOS transistor and MOS capacitor and method for manufacturing the same

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