Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
12/2002
12/12/2002US20020187636 Exposure control for phase shifting photolithographic masks
12/12/2002US20020187635 Cu film deposition equipment of semiconductor device
12/12/2002US20020187633 Capacitor and method for forming the same
12/12/2002US20020187632 Process for the formation of RuSixOy-containing barrier layers for high-k dielectrics
12/12/2002US20020187631 Copper interconnect structure having stuffed diffusion barrier
12/12/2002US20020187630 Semiconductor device with self-aligned contact and method for manufacturing the device
12/12/2002US20020187629 Method for dual damascene process without using gap-filling materials
12/12/2002US20020187628 Low k interlevel dielectric layer fabrication methods
12/12/2002US20020187627 Method of fabricating a dual damascene structure
12/12/2002US20020187625 Semiconductor device have multiple wiring layers and method of producing the same
12/12/2002US20020187624 Method for forming metal line of semiconductor device
12/12/2002US20020187623 Compound semiconductor device with delta doped layer under etching stopper layer for decreasing resistance between active layer and ohmic electrode and process of fabrication thereof
12/12/2002US20020187622 Method for processing a surface of an SiC semiconductor layer and schottky contact
12/12/2002US20020187621 Method of manufacturing semiconductor device
12/12/2002US20020187620 Mask ROM and method for manufacturing the same
12/12/2002US20020187619 Gettering process for bonded SOI wafers
12/12/2002US20020187617 Self-aligned source pocket for flash memory cells
12/12/2002US20020187616 Method of eliminating leakage current in shallow trench isolation
12/12/2002US20020187615 Method for forming isolations in memory devices with common source lines
12/12/2002US20020187614 Methods for forming ultrashallow junctions with low sheet resistance
12/12/2002US20020187613 Method of forming memory device having capacitor including layer of high dielectric constant
12/12/2002US20020187612 Compact body for silicon-on-insulator transistors requiring no additional layout area
12/12/2002US20020187611 Methods of forming transistor gates; and methods of forming programmable read-only memory constructions
12/12/2002US20020187610 Dual gate logic device
12/12/2002US20020187609 Non-volatile memory devices and methods of fabricating the same
12/12/2002US20020187608 Method of forming a floating gate of a non-volatile memory device
12/12/2002US20020187607 Method of forming a rough (high surface area) electrode from Ti and TiN capacitors and semiconductor devices including same
12/12/2002US20020187606 Interconnect line selectively isolated from an underlying contact plug
12/12/2002US20020187605 Multiple deposition of metal layers for the fabrication of an upper capacitor electrode of a trench capacitor
12/12/2002US20020187604 Semiconductor devices and manufacturing methods thereof
12/12/2002US20020187603 Method for fabricating recessed lightly doped drain field effect transistors
12/12/2002US20020187602 Method of manufacturing semiconductor device
12/12/2002US20020187600 Semiconductor structure exhibiting reduced leakage current and method of fabricating same
12/12/2002US20020187599 Process and manufacturing tool architecture for use in the manufacture of one or more protected metallization structures on a workpiece
12/12/2002US20020187598 DRAM device and method of manufacturing the same
12/12/2002US20020187597 Semiconductor device with vertical MOSFET and method of fabricating same
12/12/2002US20020187596 Method of manufacturing a semiconductor integrated circuit device
12/12/2002US20020187595 Methods for silicon-on-insulator (SOI) manufacturing with improved control and site thickness variations and improved bonding interface quality
12/12/2002US20020187594 Method of manufacturing a semiconductor device
12/12/2002US20020187593 Wafer scale processing
12/12/2002US20020187592 Method for forming a thin-film transistor
12/12/2002US20020187591 Packaging process for semiconductor package
12/12/2002US20020187590 Ball grid array packages with thermally conductive containers
12/12/2002US20020187589 Die bonding sheet sticking apparatus and method of sticking die bonding sheet
12/12/2002US20020187587 Method of manufacturing a semiconductor structure having stacked semiconductor devices
12/12/2002US20020187586 Multi chip semiconductor package and method of construction
12/12/2002US20020187585 Ball grid array module and method of manufacturing same
12/12/2002US20020187584 Two-stage transfer molding method to encapsulate mmc module
12/12/2002US20020187581 Method of reducing leakage current of a photodiode
12/12/2002US20020187578 Method for manufacturing memory device
12/12/2002US20020187577 Semiconductor laser device and process for producing the same
12/12/2002US20020187574 Method of manufacturing array substrate for use in liquid crystal display device
12/12/2002US20020187573 Method of deforming a pattern and semiconductor device formed by utilizing deformed pattern
12/12/2002US20020187572 Manufacturing method of thin film transistor panel
12/12/2002US20020187569 Silicon crystallization method
12/12/2002US20020187568 Forming semiconductor structures including acticated acceptors in buried p-type gan layers
12/12/2002US20020187566 Method for gettering semiconductor device
12/12/2002US20020187442 Yield and line width performance for liquid polymers and other materials
12/12/2002US20020187440 Printing fine pattern and masking pattern overcoating substrate; exposure to light source
12/12/2002US20020187439 Process for producing acid sensitive liquid composition containing a carbonate
12/12/2002US20020187434 Process for device fabrication in which the size of lithographically produced features is subsequently reduced
12/12/2002US20020187431 Using two masks; stripe shapes
12/12/2002US20020187423 Substrate treating method
12/12/2002US20020187420 Novel copolymers and photoresist compositions
12/12/2002US20020187419 Photoresist composition for deep ultraviolet lithography
12/12/2002US20020187407 Using ultraviolet radiation; prevention polarization; lithography patterns
12/12/2002US20020187405 Ion-beam deposition process for manufacturing attenuated phase shift photomask blanks
12/12/2002US20020187359 Ceramic electrolytic cell
12/12/2002US20020187356 Reducing stresses; noncracking; semiconductor
12/12/2002US20020187355 High speed electroplating; uniform deposits
12/12/2002US20020187334 Two-metal tab tape, double-sided csp tape, bga tape and method for manufacturing the same
12/12/2002US20020187319 Electrical device having metal pad bonded with metal wiring and manufacturing method thereof
12/12/2002US20020187266 Metal film pattern and manufacturing method thereof
12/12/2002US20020187262 Purge heater design and process development for the improvement of low k film properties
12/12/2002US20020187261 Using an Atomic Layer Deposition
12/12/2002US20020187256 Atomic Layer Deposition using a boron compound as a reducing agent.
12/12/2002US20020187255 Method of fabricating organic electroluminescent display
12/12/2002US20020187025 Transportable container including an internal environment monitor
12/12/2002US20020187024 Apparatus for storing and moving a carrier
12/12/2002US20020187023 Vertical type wafer supporting jig
12/12/2002US20020186967 Heating member for combination heating and chilling apparatus, and methods
12/12/2002US20020186736 Method for fabricating semiconductor device and semiconductor device
12/12/2002US20020186613 Apparatus and method for supplying chemicals
12/12/2002US20020186607 Sense amplifier and architecture for open digit arrays
12/12/2002US20020186602 Semiconductor device capable of adjusting internal potential
12/12/2002US20020186601 Method for fabricating cell plugs of semiconductor device
12/12/2002US20020186589 Nonvolatile semiconductor memory device
12/12/2002US20020186583 Recessed magnetic storage element and method of formation
12/12/2002US20020186582 Cladded read conductor for a pinned-on-the-fly soft reference layer
12/12/2002US20020186581 Semiconductor memory device with memory cells operated by boosted voltage
12/12/2002US20020186549 Alternative method used to package multi media card by transfer molding
12/12/2002US20020186518 Overvoltage protection circuit
12/12/2002US20020186479 Optical system
12/12/2002US20020186462 Optical imaging system with polarizer and a crystalline-quartz plate for use therewith
12/12/2002US20020186381 Method and apparatus for detecting the thickness of copper oxide
12/12/2002US20020186374 Apparatus and method for feature edge detection in semiconductor processing
12/12/2002US20020186359 Lithography system and method for device manufacture
12/12/2002US20020186357 Electron beam exposure apparatus, reduction projection system, and device manufacturing method
12/12/2002US20020186356 Optical proximity correction method utilizing gray bars as sub-resolution assist features
12/12/2002US20020186355 Projection optical system, projection exposure apparatus, and projection exposure method
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