Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
01/2003
01/07/2003US6503840 Process for forming metal-filled openings in low dielectric constant dielectric material while inhibiting via poisoning
01/07/2003US6503837 Method of rinsing residual etching reactants/products on a semiconductor wafer
01/07/2003US6503836 Method and apparatus for manufacturing semiconductor device
01/07/2003US6503835 Method of making an organic copper diffusion barrier layer
01/07/2003US6503834 Process to increase reliability CuBEOL structures
01/07/2003US6503833 Self-aligned silicide (salicide) process for strained silicon MOSFET ON SiGe and structure formed thereby
01/07/2003US6503832 Application of controlling gas valves to reduce particles from CVD process
01/07/2003US6503831 Method of forming an electronic device
01/07/2003US6503830 Method of manufacturing a semiconductor device
01/07/2003US6503829 Metal via contact of a semiconductor device and method for fabricating the same
01/07/2003US6503828 Process for selective polishing of metal-filled trenches of integrated circuit structures
01/07/2003US6503827 Method of reducing planarization defects
01/07/2003US6503826 Semiconductor device and method for manufacturing the same
01/07/2003US6503825 Method for forming multi-layer wiring structure
01/07/2003US6503824 Forming conductive layers on insulators by physical vapor deposition
01/07/2003US6503823 Method for manufacturing capacitor elements on a semiconductor substrate
01/07/2003US6503822 Methods for insitu plasma pre-deposition wafer treatment in chemical vapor deposition technology for semiconductor integrated circuit applications
01/07/2003US6503821 Integrated circuit chip carrier assembly
01/07/2003US6503820 Die pad crack absorption system and method for integrated circuit chip fabrication
01/07/2003US6503819 Fabrication process of a semiconductor integrated circuit device
01/07/2003US6503818 Delamination resistant multi-layer composite dielectric layer employing low dielectric constant dielectric material
01/07/2003US6503817 Method for establishing dopant profile to suppress silicidation retardation effect in CMOS process
01/07/2003US6503815 Method for reducing stress and encroachment of sidewall oxide layer of shallow trench isolation
01/07/2003US6503814 Method for forming trench isolation
01/07/2003US6503813 Method and structure for forming a trench in a semiconductor substrate
01/07/2003US6503812 Fabrication process for a semiconductor device with an isolated zone
01/07/2003US6503811 Substrate having a semiconductor layer, and method for fabricating the same
01/07/2003US6503810 Forming storage electrode on semiconductor wafer; nitriding;overcoating with dielectric
01/07/2003US6503809 Method and system for emitter partitioning for SiGe RF power transistors
01/07/2003US6503808 Lateral bipolar transistor and method for producing the same
01/07/2003US6503807 MOS transistor with two empty side slots on its gate and its method of formation
01/07/2003US6503806 Method for forming gate electrode of a semiconductor device with dual spacer to protect metal portion of gate
01/07/2003US6503805 Channel implant through gate polysilicon
01/07/2003US6503804 Method of manufacturing a semiconductor device
01/07/2003US6503803 Method of fabricating a semiconductor integrated circuit device for connecting semiconductor region and electrical wiring metal via titanium silicide layer
01/07/2003US6503802 Method of fabricating isolation structure for semiconductor device
01/07/2003US6503801 Non-uniform channel profile via enhanced diffusion
01/07/2003US6503800 Manufacturing method of semiconductor device having different gate oxide thickness
01/07/2003US6503799 Method of manufacturing semiconductor device
01/07/2003US6503798 Low resistance strap for high density trench DRAMS
01/07/2003US6503797 Nonvolatile semiconductor storage apparatus and production method of the same
01/07/2003US6503796 Method and structure for a top plate design for making capacitor-top-plate to bit-line-contact overlay margin
01/07/2003US6503795 Method for fabricating a semiconductor device having a storage cell
01/07/2003US6503794 Semiconductor integrated circuit device and method for manufacturing the same
01/07/2003US6503793 Method for concurrently forming an ESD protection device and a shallow trench isolation region
01/07/2003US6503792 Method for fabricating a patterned metal-oxide-containing layer
01/07/2003US6503791 Method of manufacturing semiconductor devices utilizing underlayer-dependency of deposition of capacitor electrode film, and semiconductor device
01/07/2003US6503789 Contact structure for a semiconductor device and manufacturing method thereof
01/07/2003US6503788 Semiconductor device and method of manufacture thereof
01/07/2003US6503787 Device and method for forming semiconductor interconnections in an integrated circuit substrate
01/07/2003US6503785 Flash memory cell with contactless bit line, and process of fabrication
01/07/2003US6503784 Double gated transistor
01/07/2003US6503783 SOI CMOS device with reduced DIBL
01/07/2003US6503782 Complementary accumulation-mode JFET integrated circuit topology using wide (>2eV) bandgap semiconductors
01/07/2003US6503781 Molded ball grid array
01/07/2003US6503780 Wafer scale image sensor package fabrication method
01/07/2003US6503779 Method of manufacturing flip chip type semiconductor device
01/07/2003US6503778 Thin film device and method of manufacturing the same
01/07/2003US6503774 Embedding parasitic model for pi-fet layouts
01/07/2003US6503773 Low threading dislocation density relaxed mismatched epilayers without high temperature growth
01/07/2003US6503772 Method of manufacturing a thin film transistor-integrated color filter
01/07/2003US6503771 Semiconductor photoelectrically sensitive device
01/07/2003US6503768 Method for monolithic integration of multiple devices on an optoelectronic substrate
01/07/2003US6503767 Process for monitoring a process, planarizing a surface, and for quantifying the results of a planarization process
01/07/2003US6503765 Testing vias and contacts in integrated circuit fabrication
01/07/2003US6503764 Method of making in high density DRAM circuit having a stacked capacitor
01/07/2003US6503763 Method of making MFMOS capacitors with high dielectric constant materials
01/07/2003US6503693 UV assisted chemical modification of photoresist
01/07/2003US6503689 Crosslinked polymeric particles including one or more chromophore units such as anthracenyl methacrylate; relief images
01/07/2003US6503688 A coating layer containing a polysubstituted triphenylene compound on the substrate surface, the polysubstituted triphenylene compound being an electron beam resist material
01/07/2003US6503687 Alicyclic photosensitive polymer, resist composition containing the same and method of preparing the resist composition
01/07/2003US6503686 Photoresists are comprised of a fluoroalcohol functional group and a nitrile-containing compound which together simultaneously mpart high ultraviolet (UV) transparency and developability in basic media
01/07/2003US6503682 Photoresist composition, preparation method thereof and method for forming a pattern during semiconductor processing using the photoresist composition
01/07/2003US6503671 Lithography system for accomplishing a smaller size and higher performance of a semiconductor device
01/07/2003US6503667 Method for fabricating mask
01/07/2003US6503666 Phase shift masking for complex patterns
01/07/2003US6503665 Phase shift mask and semiconductor device fabricated with the phase shift mask
01/07/2003US6503664 Thin film materials for the preparation of attenuating phase shift masks
01/07/2003US6503641 Interconnects with Ti-containing liners
01/07/2003US6503633 Composition for film formation, process for producing composition for film formation, method of film formation, and silica-based film
01/07/2003US6503626 Graphite-based heat sink
01/07/2003US6503610 Having low dislocation density without increasing thickness of mask layer; regrowth of masking layer continues until disappearance of underlying crystal
01/07/2003US6503609 Dielectric layer provided between said first electrode and second electrode and a barrier layer provided between said first electrode and said dielectric layer
01/07/2003US6503594 Silicon wafers having controlled distribution of defects and slip
01/07/2003US6503570 Cyclosilane compound, and solution composition and process for forming a silicon film
01/07/2003US6503562 Semiconductor fabrication apparatus and fabrication method thereof
01/07/2003US6503561 Liquid precursor mixtures for deposition of multicomponent metal containing materials
01/07/2003US6503464 Ultraviolet processing apparatus and ultraviolet processing method
01/07/2003US6503433 Liquid transfer molding system for encapsulating semiconductor integrated circuits
01/07/2003US6503418 Ta barrier slurry containing an organic additive
01/07/2003US6503380 Physical vapor target constructions
01/07/2003US6503375 Electroplating apparatus using a perforated phosphorus doped consumable anode
01/07/2003US6503374 Simultaneously sputtering strontium, bismuth, tantalum and niobium mixed oxide and bismuth oxide targets at different radio frequency powers to form semiconductor dielectric film
01/07/2003US6503368 Substrate support having bonded sections and method
01/07/2003US6503367 Magnetically enhanced inductively coupled plasma reactor with magnetically confined plasma
01/07/2003US6503365 Multi-chamber system having compact installation set-up for an etching facility for semiconductor device manufacturing
01/07/2003US6503364 Plasma processing apparatus
01/07/2003US6503363 System for reducing wafer contamination using freshly, conditioned alkaline etching solution
01/07/2003US6503361 Polishing method and polishing apparatus using the same
01/07/2003US6503360 Etching method and apparatus