Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
01/2003
01/16/2003WO2003005435A1 Substrate treating device and substrate treating method, substrate flattening method
01/16/2003WO2003005434A2 Method for reducing surface rugosity of a semiconductor slice
01/16/2003WO2003005433A2 Integrated circuit device including a layered superlattice material with an interface buffer layer
01/16/2003WO2003005432A1 Method and apparatus for forming film having low dielectric constant, and electronic device using the film
01/16/2003WO2003005431A1 Chemical mechanical polishing slurry for semiconductor integrated circuit, polishing method and semiconductor integrated circuit
01/16/2003WO2003005430A2 Method and apparatus for controlling a plating process
01/16/2003WO2003005429A1 Method for preparing low dielectric films
01/16/2003WO2003005427A1 Processing system and cleaning method
01/16/2003WO2003005426A1 Semiconductor structure with temperature control device
01/16/2003WO2003005425A1 Semiconductor layer formation utilizing laser irradiation
01/16/2003WO2003005424A1 Coating device and coating method
01/16/2003WO2003005423A1 Substrate processing apparatus
01/16/2003WO2003005422A2 Datum plate for use in installations of substrate handling systems
01/16/2003WO2003005421A2 Fabricating structures using chemo-mechanical polishing and chemically-selective endpoint detection
01/16/2003WO2003005420A2 Method and apparatus for fabricating structures using chemically selective endpoint detection
01/16/2003WO2003005418A2 Assembly for manipulating and/or storing a mask and/or a substrate
01/16/2003WO2003005416A2 Trench structure for semiconductor devices
01/16/2003WO2003005414A2 Power mosfet with deep implanted junctions
01/16/2003WO2003005413A2 Fast swap dual substrate transport for load lock
01/16/2003WO2003005412A2 Method and apparatus for production line screening
01/16/2003WO2003005411A2 Method for producing a stepped structure on a substrate
01/16/2003WO2003005396A2 Method and apparatus for scanned instrument calibration
01/16/2003WO2003005385A1 Capacitor having improved electrodes
01/16/2003WO2003005377A2 Passivating overcoat bilayer
01/16/2003WO2003005296A1 An injection moulded product and a method for its manufacture
01/16/2003WO2003005128A1 Sensor for determining radiated energy and use thereof
01/16/2003WO2003005124A1 A stamp having an antisticking layer and a method of forming of repairing such a stamp
01/16/2003WO2003005115A1 An etchant for a wire, a method for manufacturing the wire and a method for manufacturing a thin film transistor array panel including the method
01/16/2003WO2003005097A1 Projection optical system and exposure device having the projection optical system
01/16/2003WO2003004967A1 Position detection apparatus, position detection method, and electr5onic part convey apparatus
01/16/2003WO2003004966A1 Interferometry system and method employing an angular difference in propagation between orthogonally polarized input beam components
01/16/2003WO2003004722A1 Method for cleaning reaction container and film deposition system
01/16/2003WO2003004719A1 Mask and substrate holder arrangement
01/16/2003WO2003004386A1 System and method for manufacturing flat display panel
01/16/2003WO2003004180A1 Substrate handling end effector
01/16/2003WO2003003982A2 Light-emitting nanoparticles and method of making same
01/16/2003WO2002089188A3 Semiconductor structures utilizing binary metal oxide layers
01/16/2003WO2002086959A3 Post-planarization clean-up
01/16/2003WO2002074445A8 Atomizer
01/16/2003WO2002061797A3 Icp window heater integrated with faraday shield or floating electrode between the source power coil and the icp window
01/16/2003WO2002056348A3 Method for incorporating silicon into cvd metal films
01/16/2003WO2002054470A3 Method for contacting a doping area on a semiconductor element
01/16/2003WO2002054407A3 Mram write apparatus and method
01/16/2003WO2002048434A3 Gallium nitride materials and methods for forming layers thereof
01/16/2003WO2002043104A3 Hybrid scanning system and methods for ion implantation
01/16/2003WO2002041080A3 Process for reducing edge roughness in patterned photoresist
01/16/2003WO2002035300A3 Method and apparatus for embedded process control framework in tool systems
01/16/2003WO2002029819A3 An analog functional module using magnetoresistive memory technology
01/16/2003WO2002027805A3 A theory of the charge multiplication process in avalanche photodiodes
01/16/2003WO2002027404A3 Mitigation of multilayer defects on a reticle
01/16/2003WO2002009151A3 Magnetoresistive structure
01/16/2003WO2001083844A3 Method for depositing metal and metal oxide films and patterned films
01/16/2003WO2001073836A9 Method for modifying the surface of a fluorocarbon
01/16/2003WO2001054176A9 Wafer bonding techniques to minimize built-in stress of silicon microstructures and micro-mirrors
01/16/2003US20030014730 Transfer mask blank, transfer mask and exposure method
01/16/2003US20030014729 Database for designing integrated circuit device and method for designing integrated circuit device
01/16/2003US20030014726 Method of wiring semiconductor integrated circuit, semiconductor integrated circuit, and computer product
01/16/2003US20030014725 Electronic circuit designing method and apparatus, and storage medium
01/16/2003US20030014724 Method for distributing clock signals to flip-flop circuits
01/16/2003US20030014722 Automatic layout design method of wirings in semiconductor integrated circuit
01/16/2003US20030014720 Timing budget designing method
01/16/2003US20030014719 Method of designing hierarchical layout of semiconductor integrated circuit, and computer product
01/16/2003US20030014704 Test apparatus for semiconductor devices having bult-in self-test function
01/16/2003US20030014689 Flash EEprom system
01/16/2003US20030014205 Methods and apparatus for semiconductor testing
01/16/2003US20030014197 Method and apparatus for wafer analysis
01/16/2003US20030014158 Alignment of semiconductor wafers and other articles
01/16/2003US20030014157 Method for determining a position of a robot
01/16/2003US20030014155 High temperature substrate transfer robot
01/16/2003US20030014145 Integration of fault detection with run-to-run control
01/16/2003US20030014144 Feed-forward control of tci doping for improving mass-production-wise, statistical distribution of critical performance parameters in semiconductor devices
01/16/2003US20030013416 Radio architecture
01/16/2003US20030013394 Polishing pad conditioner for semiconductor polishing apparatus and method of monitoring the same
01/16/2003US20030013391 Polishing apparatus
01/16/2003US20030013387 Barrier removal at low polish pressure
01/16/2003US20030013386 Chemical mechanical polishing compositions and methods relating thereto
01/16/2003US20030013385 Nitride CMP slurry having selectivity to nitride
01/16/2003US20030013380 Semiconductor wafer dividing method
01/16/2003US20030013328 Connection assembly for integrated circuit sensors
01/16/2003US20030013323 Method of selective removal of SiGe alloys
01/16/2003US20030013322 High speed pick and place apparatus
01/16/2003US20030013321 Anneal wafer manufacturing mehtod and anneal wafer
01/16/2003US20030013320 Method of forming a thin film using atomic layer deposition
01/16/2003US20030013319 Semiconductor structure with selective doping and process for fabrication
01/16/2003US20030013318 Apparatus and method for forming a combined substrate structure
01/16/2003US20030013317 Method and apparatus for etching a semiconductor die
01/16/2003US20030013316 Method of forming wiring using a dual damascene process
01/16/2003US20030013315 Process chamber used in manufacture of semiconductor device, capable of reducing contamination by particulates
01/16/2003US20030013314 Method of reducing particulates in a plasma etch chamber during a metal etch process
01/16/2003US20030013313 Process for fabricating semiconductor device
01/16/2003US20030013312 Method of reducing particle density in a cool down chamber
01/16/2003US20030013311 Method of avoiding dielectric layer deterioation with a low dielectric constant during a stripping process
01/16/2003US20030013310 Method of washing a semiconductor wafer
01/16/2003US20030013309 Dual depth trench isolation
01/16/2003US20030013308 Method for minimizing variation in etch rate of semiconductor wafer caused by variation in mask pattern density
01/16/2003US20030013307 Method of fabricating a self-aligned landing via
01/16/2003US20030013306 Barrier to prevent copper diffusion; polishing using reducing agent
01/16/2003US20030013305 Method of producing semiconductor device and semiconductor substrate
01/16/2003US20030013303 Full image exposure of field with alignment marks
01/16/2003US20030013302 Multilayered copper structure for improving adhesion property