| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 01/21/2003 | US6510074 Ferroelectric memory having a BaTiO3 recording layer oriented in a <111> direction |
| 01/21/2003 | US6510073 Two transistor ferroelectric non-volatile memory |
| 01/21/2003 | US6510072 Nonvolatile ferroelectric memory device and method for detecting weak cell using the same |
| 01/21/2003 | US6509971 Interferometer system |
| 01/21/2003 | US6509970 Wavelength monitoring apparatus for laser light for semiconductor exposure |
| 01/21/2003 | US6509960 Generating signal indicative of intensity of emanated light |
| 01/21/2003 | US6509957 Stage device and exposure apparatus |
| 01/21/2003 | US6509956 Projection exposure method, manufacturing method for device using same, and projection exposure apparatus |
| 01/21/2003 | US6509952 Method and system for selective linewidth optimization during a lithographic process |
| 01/21/2003 | US6509951 Lithographic projection apparatus having a temperature controlled heat shield |
| 01/21/2003 | US6509942 Liquid crystal display device, wiring substrate, and methods for fabricating the same |
| 01/21/2003 | US6509759 Multi power supply circuit protection apparatus and method |
| 01/21/2003 | US6509750 Apparatus for detecting defects in patterned substrates |
| 01/21/2003 | US6509739 Method for locating defects and measuring resistance in a test structure |
| 01/21/2003 | US6509650 Electronic device, and method of patterning a first layer |
| 01/21/2003 | US6509649 Semiconductor device and fabricating method thereof |
| 01/21/2003 | US6509648 Multilayer semiconductor device |
| 01/21/2003 | US6509647 Apparatus and methods of testing and assembling bumped devices using an anisotropically conductive layer |
| 01/21/2003 | US6509643 Tab tape with stiffener and semiconductor device using same |
| 01/21/2003 | US6509634 Chip mounting structure having adhesive conductor |
| 01/21/2003 | US6509631 Semiconductor device and liquid crystal module |
| 01/21/2003 | US6509628 IC chip |
| 01/21/2003 | US6509627 Flowable germanium doped silicate glass for use as a spacer oxide |
| 01/21/2003 | US6509626 Conductive device components of different base widths formed from a common conductive layer |
| 01/21/2003 | US6509625 Guard structure for bipolar semiconductor device |
| 01/21/2003 | US6509624 Semiconductor fuses and antifuses in vertical DRAMS |
| 01/21/2003 | US6509623 Microelectronic air-gap structures and methods of forming the same |
| 01/21/2003 | US6509622 Structures that reduce or prevent damage to integrated circuits. |
| 01/21/2003 | US6509621 Magnetic random access memory capable of writing information with reduced electric current |
| 01/21/2003 | US6509619 Detectors |
| 01/21/2003 | US6509618 Device having thin first spacers and partially recessed thick second spacers for improved salicide resistance on polysilicon gates |
| 01/21/2003 | US6509616 Semiconductor device and its manufacturing method |
| 01/21/2003 | US6509615 Semiconductor device having dynamic threshold transistors and element isolation region and fabrication method thereof |
| 01/21/2003 | US6509614 TFT-LCD formed with four masking steps |
| 01/21/2003 | US6509613 Self-aligned floating body control for SOI device through leakage enhanced buried oxide |
| 01/21/2003 | US6509612 High dielectric constant materials as gate dielectrics (insulators) |
| 01/21/2003 | US6509611 Method for wrapped-gate MOSFET |
| 01/21/2003 | US6509609 Grooved channel schottky MOSFET |
| 01/21/2003 | US6509608 Trench-gate field-effect transistors and their manufacture |
| 01/21/2003 | US6509607 Semiconductor device with reduced source diffusion distance and method of making same |
| 01/21/2003 | US6509605 Flash memory cell having a flexible element |
| 01/21/2003 | US6509604 Nitridation barriers for nitridated tunnel oxide for circuitry for flash technology and for LOCOS/STI isolation |
| 01/21/2003 | US6509602 Nonvolatile memory and manufacturing method thereof |
| 01/21/2003 | US6509601 Semiconductor memory device having capacitor protection layer and method for manufacturing the same |
| 01/21/2003 | US6509600 Flash memory cell |
| 01/21/2003 | US6509599 Trench capacitor with insulation collar and method for producing the trench capacitor |
| 01/21/2003 | US6509597 Ferroelectric memory device |
| 01/21/2003 | US6509595 DRAM cell fabricated using a modified logic process and method for operating same |
| 01/21/2003 | US6509594 Semiconductor memory device having MFMIS transistor and increased data storage time |
| 01/21/2003 | US6509593 Semiconductor device and method of manufacturing the same |
| 01/21/2003 | US6509592 Ferroelectric memory |
| 01/21/2003 | US6509587 Semiconductor device |
| 01/21/2003 | US6509586 Semiconductor device, method for fabricating the semiconductor device and semiconductor integrated circuit |
| 01/21/2003 | US6509583 Semiconductor device formed on insulating layer and method of manufacturing the same |
| 01/21/2003 | US6509579 Semiconductor device |
| 01/21/2003 | US6509577 Systems and methods for exposing substrate periphery |
| 01/21/2003 | US6509572 Charged particle beam lithography apparatus for forming pattern on semi-conductor |
| 01/21/2003 | US6509571 Proximity exposure method by oblique irradiation with light |
| 01/21/2003 | US6509568 Electrostatic deflector for electron beam exposure apparatus |
| 01/21/2003 | US6509546 Laser excision of laminate chip carriers |
| 01/21/2003 | US6509542 Voltage control sensor and control interface for radio frequency power regulation in a plasma reactor |
| 01/21/2003 | US6509415 Low dielectric constant organic dielectrics based on cage-like structures |
| 01/21/2003 | US6509386 Porous insulating composition comprising the steps of (A) providing at least one organic sacrificial material/dielectric material composition comprising at least one organic sacrificial material and at least one dielectric |
| 01/21/2003 | US6509283 Thermal oxidation method utilizing atomic oxygen to reduce dangling bonds in silicon dioxide grown on silicon |
| 01/21/2003 | US6509282 Silicon-starved PECVD method for metal gate electrode dielectric spacer |
| 01/21/2003 | US6509281 Techniques for improving adhesion of silicon dioxide to titanium |
| 01/21/2003 | US6509280 Method for forming a dielectric layer of a semiconductor device |
| 01/21/2003 | US6509279 Methods for processing a coating film and for manufacturing a semiconductor element |
| 01/21/2003 | US6509278 Method of forming a semiconductor contact that includes selectively removing a Ti-containing layer from the surface |
| 01/21/2003 | US6509277 Method of manufacturing semiconductor integrated circuit device having insulatro film formed from liquid containing polymer of silicon, oxygen, and hydrogen |
| 01/21/2003 | US6509276 Focused ion beam etching of copper with variable pixel spacing |
| 01/21/2003 | US6509275 Method of manufacturing thin film and pretreating method thereof |
| 01/21/2003 | US6509274 Method for forming aluminum lines over aluminum-filled vias in a semiconductor substrate |
| 01/21/2003 | US6509273 Method for manufacturing a semiconductor device |
| 01/21/2003 | US6509272 Positioning pad for contact with wafer surface and planarizing surface using pad and fluid composition including a chelating agent |
| 01/21/2003 | US6509271 Manufacturing method of semiconductor device |
| 01/21/2003 | US6509270 Method for polishing a semiconductor topography |
| 01/21/2003 | US6509269 Elimination of pad glazing for Al CMP |
| 01/21/2003 | US6509268 Thermal densification in the early stages of copper MOCVD for depositing high quality Cu films with good adhesion and trench filling characteristics |
| 01/21/2003 | US6509267 Method of forming low resistance barrier on low k interconnect with electrolessly plated copper seed layer |
| 01/21/2003 | US6509266 Halogen addition for improved adhesion of CVD copper to barrier |
| 01/21/2003 | US6509265 Process for manufacturing a contact barrier |
| 01/21/2003 | US6509264 Method to form self-aligned silicide with reduced sheet resistance |
| 01/21/2003 | US6509263 Method for fabricating a semiconductor memory device having polysilicon with an enhanced surface concentration and reduced contact resistance |
| 01/21/2003 | US6509262 Method of reducing electromigration in copper lines by calcium-doping copper surfaces in a chemical solution |
| 01/21/2003 | US6509261 Wiring forming method |
| 01/21/2003 | US6509260 Method of shallow trench isolation using a single mask |
| 01/21/2003 | US6509259 Lower layer comprises a non-silicon containing organic polymer and an upper layer comprises an organic, silicon containing polymer |
| 01/21/2003 | US6509258 Etch stop in damascene interconnect structure and method of making |
| 01/21/2003 | US6509257 Semiconductor device and process for making the same |
| 01/21/2003 | US6509256 Methods of forming electrically conductive interconnections and electrically interconnected substrates |
| 01/21/2003 | US6509255 Fuse area structure having guard ring surrounding fuse opening in semiconductor device and method of forming the same |
| 01/21/2003 | US6509254 Method of forming electrode structure and method of fabricating semiconductor device |
| 01/21/2003 | US6509253 T-shaped gate electrode for reduced resistance |
| 01/21/2003 | US6509252 Method of manufacturing semiconductor device |
| 01/21/2003 | US6509251 Method of forming a resist pattern for blocking implantation of an impurity into a semiconductor substrate |
| 01/21/2003 | US6509250 Method for CMOS well drive in a non-inert ambient |
| 01/21/2003 | US6509249 Method of fabricating shallow trench isolation |
| 01/21/2003 | US6509248 Fabrication of semiconductor gettering structures by ion implantation |
| 01/21/2003 | US6509247 Semiconductor device and alignment method |