Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
03/2003
03/27/2003US20030058435 Method of reviewing detected defects
03/27/2003US20030058433 Defect detection with enhanced dynamic range
03/27/2003US20030058429 Stable energy detector for extreme ultraviolet radiation detection
03/27/2003US20030058428 Controlling a photolithography process by computer, manufacturing semiconductor devices; data processing based on an algorithm for evaluating a correction value of a stepper
03/27/2003US20030058422 Lithographic apparatus and device manufacturing method
03/27/2003US20030058417 Environmental control chamber
03/27/2003US20030058399 Field sequential liquid crystal display apparatus using active matrix liquid crystal display device
03/27/2003US20030058378 Thin film transistor crystal liquid display device including plural conductive beads and manufacturing method thereof
03/27/2003US20030058376 Liquid crystal display device and method of manufacturing the same
03/27/2003US20030058374 Liquid crystal display and method of manufacturing the same
03/27/2003US20030058029 Voltage boosting circuit with two main charge pumps
03/27/2003US20030058027 Circuits and methods for electrostatic discharge protection in integrated circuits
03/27/2003US20030058025 Integrated electronic circuit including non-linear inductor devices
03/27/2003US20030058020 Semiconductor device capable of reducing noise to signal line
03/27/2003US20030058016 Operation control according to temperature variation in integrated circuit
03/27/2003US20030057988 Semiconductor device inspecting method using conducting AFM
03/27/2003US20030057979 Wafer probe station for low-current measurements
03/27/2003US20030057978 Substrate for a probe card having conductive layers for supplying power to IC devices
03/27/2003US20030057976 Probe card
03/27/2003US20030057975 Segmented contactor
03/27/2003US20030057971 Inspection method using a charged particle beam and inspection device based thereon
03/27/2003US20030057966 Electromagnetic interference analysis method and apparatus
03/27/2003US20030057957 Method for chemically etching photo-defined micro electrical contacts
03/27/2003US20030057940 Testing apparatus including testing board having wirings connected to common point and method of testing semiconductor device by composing signals
03/27/2003US20030057856 EL display device, driving method thereof, and electronic equipment provided with the EL display device
03/27/2003US20030057848 Plasma processing apparatus
03/27/2003US20030057845 Plasma processing apparatus
03/27/2003US20030057844 Method and device for attenuating harmonics in semiconductor plasma processing systems
03/27/2003US20030057619 Method and apparatus for operating a vibration isolation system having electronic and pneumatic control systems
03/27/2003US20030057614 Method and apparatus for processing a microeletronic workpiece including an apparatus and method for executing a processing step at an elevated temperature
03/27/2003US20030057572 Encapsulation of pin solder for maintaining accuracy in pin position
03/27/2003US20030057571 Wiring modeling technique
03/27/2003US20030057569 Semiconductor device
03/27/2003US20030057568 Flip chip type semiconductor device and method of manufacturing the same
03/27/2003US20030057567 Semiconductor component and method for its production
03/27/2003US20030057564 Allows for physical separation of memory circuits and control logic circuits onto different layers such that each layer may be separately optimized
03/27/2003US20030057563 Integrated package and methods for making same
03/27/2003US20030057562 Provided with a contact plug layer connected to a semiconductor substrate and a pad electrode
03/27/2003US20030057561 Semiconductor device including porous insulating material and manufacturing method therefor
03/27/2003US20030057558 Semiconductor device and method of fabricating the same
03/27/2003US20030057557 Semiconductor device of multi-wiring structure and method of manufacturing the same
03/27/2003US20030057556 Semiconductor device including a pad and a method of manufacturing the same
03/27/2003US20030057555 Structure for contact formation using a silicon-germanium alloy
03/27/2003US20030057554 Semiconductor structure with substantially etched nitride and/or oxynitride defects protruding therefrom
03/27/2003US20030057553 Fluorine diffusion barriers for fluorinated dielectrics in integrated circuits
03/27/2003US20030057552 Semiconductor chip element, semiconductor chip element mounting structure, semiconductor chip element mounting device and mounting method
03/27/2003US20030057551 Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same
03/27/2003US20030057549 Semiconductor integrated circuit device with I/O cell and connection member
03/27/2003US20030057543 Film substrate, semiconductor device, method of manufacturing film substrate, method of manufacturing semiconductor device and method of manufacturing circuit board with semiconductor device
03/27/2003US20030057540 Combination-type 3D stacked IC package
03/27/2003US20030057538 Die attach adhesives for semiconductor applications efficient processes for producing such devices and the devices per se produced by the efficient processes
03/27/2003US20030057537 Semiconductor device
03/27/2003US20030057531 Post passivation interconnection schemes on top of the IC chips
03/27/2003US20030057529 Package for a discrete device and manufacturing method of the same
03/27/2003US20030057528 Semiconductor device with copper fuse section
03/27/2003US20030057527 Integration of barrier layer and seed layer
03/27/2003US20030057526 Integration of barrier layer and seed layer
03/27/2003US20030057525 Flexible integrated monolithic circuit
03/27/2003US20030057524 Method of fabricating a high-voltage transistor with a multi-layered extended drain structure
03/27/2003US20030057523 Semiconductor device and drive circuit using the semiconductor devices
03/27/2003US20030057522 Process to create buried heavy metal at selected depth
03/27/2003US20030057521 Semiconductor structure used for fabricating bipolar transistors and method of fabricating the same
03/27/2003US20030057519 Semiconductor device and manufacturing method therefor
03/27/2003US20030057517 Precision high-frequency capacitor formed on semiconductor substrate
03/27/2003US20030057516 Monolithic circuit inductance
03/27/2003US20030057514 Integrated circuit formed by removing undesrable second oxide while minimally affecting a desirable first oxide
03/27/2003US20030057513 Membrane IC fabrication
03/27/2003US20030057510 Capacitance element and boosting circuit using the same
03/27/2003US20030057507 CMOS-compatible metal-semiconductor-metal photodetector
03/27/2003US20030057506 Dielectric film
03/27/2003US20030057505 Semiconductor device and method of manufacturing the same
03/27/2003US20030057504 Seminconductor device and method of manufacturing the same
03/27/2003US20030057502 Semiconductor device
03/27/2003US20030057501 Semiconductor device and method of manufacturing the same
03/27/2003US20030057499 Method of manufacturing a dual gate semiconductor device with a poly-metal electrode
03/27/2003US20030057498 Semiconductor device having channel cut layers provided at different depths
03/27/2003US20030057497 Semiconductor device
03/27/2003US20030057496 Nmos esd protection device with thin silicide and methods for making same
03/27/2003US20030057494 Semiconductor device having a buried layer for reducing latchup and a method of manufacture therefor
03/27/2003US20030057493 Semiconductor device and manufacturing method therefor
03/27/2003US20030057491 Semiconductor device and method of manufacturing the same
03/27/2003US20030057490 Semiconductor device substrate and method of manufacturing semiconductor device substrate
03/27/2003US20030057489 Method for manufacturing semiconductor substrate, semiconductor substrate, electrooptic device and electronic apparatus
03/27/2003US20030057488 Potential clamping region for connecting second semiconductor layer with first semiconductor layer is formed in insulation layer in order to fix potential of body portion to potential of first semiconductor layer
03/27/2003US20030057487 Semiconductor chip having multiple functional blocks integrated in a single chip and method for fabricating the same
03/27/2003US20030057486 Fin field effect transistor with self-aligned gate
03/27/2003US20030057485 High-voltage periphery
03/27/2003US20030057484 Semiconductor device and method of manufacturing the same
03/27/2003US20030057483 Grooved planar dram transfer device using buried pocket
03/27/2003US20030057482 Semiconductor device and method for manufacturing thereof
03/27/2003US20030057481 Ram
03/27/2003US20030057478 Mos-gated power semiconductor device
03/27/2003US20030057477 CMOS integrated circuit having vertical transistors and a process for fabricating same
03/27/2003US20030057476 Semiconductor device
03/27/2003US20030057475 Non-volatile semiconductor memory device
03/27/2003US20030057473 Nonvolatile semiconductor memory device
03/27/2003US20030057472 Method of forming a capacitor
03/27/2003US20030057471 Top electrode barrier for on-chip die de-coupling capacitor and method of making same
03/27/2003US20030057469 Semiconductor charge pump circuit and nonvolatile semiconductor memory device
03/27/2003US20030057467 Method of forming a metal to polysilicon contact in oxygen environment