Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
04/2003
04/01/2003US6543035 LCR extraction method and computer program for performing LCR extraction in LSI design process
04/01/2003US6543033 Circuit design apparatus, circuit design method, circuit design program and semiconductor integrated circuit fabrication method
04/01/2003US6543030 Computer-implemented conversion of combination-logic module for improving timing characteristics of incorporating integrated circuit design
04/01/2003US6543018 System and method to facilitate flexible control of bus drivers during scan test operations
04/01/2003US6542839 Apparatus and method for calibrating the position of a cassette indexer
04/01/2003US6542837 Wafer processing system
04/01/2003US6542835 Data collection methods and apparatus
04/01/2003US6542830 Process control system
04/01/2003US6542783 Tool position measurement method, offset measurement method, reference member and bonding apparatus
04/01/2003US6542419 Semiconductor integrated circuit device with electrically programmable fuse
04/01/2003US6542412 Process for making and programming and operating a dual-bit multi-level ballistic flash memory
04/01/2003US6542406 Row decoder of a NOR-type flash memory device
04/01/2003US6542402 Thin film magnetic memory device capable of easily controlling a data write current
04/01/2003US6542401 SRAM device
04/01/2003US6542398 Magnetic random access memory
04/01/2003US6542396 Method and apparatus for a dense metal programmable ROM
04/01/2003US6542374 Circuit board, method for manufacturing the circuit board, and display device and electronic equipment employing the circuit board
04/01/2003US6542351 Capacitor structure
04/01/2003US6542317 Optical system for crystallization tool
04/01/2003US6542251 Illumination and imaging device for multiple spectral regions, and coordinate measuring machine having an illumination and imaging device for multiple spectral regions
04/01/2003US6542237 Using mask; accurate pattern adjustment
04/01/2003US6542224 Silica-based light-weight EUV lithography stages
04/01/2003US6542223 Scanning type exposure uniformizing system and method
04/01/2003US6542222 Beam output control method, beam output apparatus and exposure system, and device manufacturing method using the exposure system
04/01/2003US6542220 Purge gas systems for use in lithographic projection apparatus
04/01/2003US6542219 Optical correction plate, and its application in a lithographic projection apparatus
04/01/2003US6542137 With reduction in the off-current of a switching thin-film transistor (TFT) and an increase in the on-current of a current TFT in a current-drive TFT display
04/01/2003US6542005 Semiconductor integrated circuit and method of designing the same
04/01/2003US6541994 Semiconductor device with a self-testing function and a method for testing the semiconductor device
04/01/2003US6541989 Testing device for semiconductor components and a method of using the device
04/01/2003US6541983 Method for measuring fuse resistance in a fuse array
04/01/2003US6541956 Carrier identification system, carrier identification method and storage media
04/01/2003US6541874 Encapsulation of microelectronic assemblies
04/01/2003US6541872 Multi-layered adhesive for attaching a semiconductor die to a substrate
04/01/2003US6541871 Method for fabricating a stacked chip package
04/01/2003US6541867 Microelectronic connector with planar elastomer sockets
04/01/2003US6541866 Cobalt barrier for nickel silicidation of a gate electrode
04/01/2003US6541865 Porous dielectric material and electronic devices fabricated therewith
04/01/2003US6541864 Thickness of a first insulation film corresponds to the depth of a contact hole and a surface of a second insulation film serves as a bottom face of a wire groove; prevents short circuiting even when an interval between wires is reduced
04/01/2003US6541863 Layer of porous silicon having lower density than the solid silicon starting material, and having conductive interconnections formed therein; stray capacitance of adjacent wiring lines is reduced
04/01/2003US6541862 Semiconductor device including a plurality of interconnection layers, manufacturing method thereof and method of designing semiconductor circuit used in the manufacturing method
04/01/2003US6541861 Semiconductor device manufacturing method including forming step of SOI structure and semiconductor device having SOI structure
04/01/2003US6541860 Barrier-to-seed layer alloying in integrated circuit interconnects
04/01/2003US6541859 Methods and structures for silver interconnections in integrated circuits
04/01/2003US6541858 Interconnect alloys and methods and apparatus using same
04/01/2003US6541857 Method of forming BGA interconnections having mixed solder profiles
04/01/2003US6541854 Super low profile package with high efficiency of heat dissipation
04/01/2003US6541852 Flexible sheet bonded in tension on a rigid frame so that the sheet spans an aperture in the frame; frame and sheet have different coefficients of thermal expansion; use making microelectronics
04/01/2003US6541848 Semiconductor device including stud bumps as external connection terminals
04/01/2003US6541843 Anti-reflective coatings and methods for forming and using same
04/01/2003US6541842 Metal barrier behavior by SiC:H deposition on porous materials
04/01/2003US6541841 Semiconductor device including high frequency circuit with inductor
04/01/2003US6541840 On-chip capacitor
04/01/2003US6541839 Microelectronics structure comprising a low voltage part provided with protection against a high voltage part and method for obtaining said protection
04/01/2003US6541837 Charge-coupled device wafer cover plate with compact interconnect wiring
04/01/2003US6541830 Titanium boride gate electrode and interconnect
04/01/2003US6541829 Semiconductor device and method of manufacturing the same
04/01/2003US6541828 Dielectric layers over the gate oxide layer and word lines are aligned with the bit lines in the substrate, and openings at intersections between parallel word lines and dielectric layers expose the gate oxide layer
04/01/2003US6541826 Field effect semiconductor device and its production method
04/01/2003US6541825 Semiconductor device including impurity layer having continuous portions formed at different depths and method of manufacturing the same
04/01/2003US6541823 Semiconductor device including multiple field effect transistors and manufacturing method thereof
04/01/2003US6541822 Method of manufacturing an SOI type semiconductor that can restrain floating body effect
04/01/2003US6541821 SOI device with source/drain extensions and adjacent shallow pockets
04/01/2003US6541819 Semiconductor device having non-power enhanced and power enhanced metal oxide semiconductor devices and a method of manufacture therefor
04/01/2003US6541818 Field-effect transistor configuration with a trench-shaped gate electrode and an additional highly doped layer in the body region
04/01/2003US6541817 Trench-gate semiconductor devices and their manufacture
04/01/2003US6541816 Planar structure for non-volatile memory devices
04/01/2003US6541815 High-density dual-cell flash memory structure
04/01/2003US6541813 Having a dielectric film containing at least either barium and/or strontium with titanium oxide, for example barium titanate, strontium titanate or barium strontium titanate; suppresses leakage current
04/01/2003US6541812 Capacitor and method for forming the same
04/01/2003US6541811 Capacitor/antifuse structure having a barrier-layer electrode and improved barrier layer
04/01/2003US6541810 Modified vertical MOSFET and methods of formation thereof
04/01/2003US6541809 Method of making straight wall containers and the resultant containers
04/01/2003US6541808 Contact structure for semiconductor devices and corresponding manufacturing process
04/01/2003US6541807 Semiconductor device having capacitor and method of manufacturing the same
04/01/2003US6541806 Ferroelectric device with capping layer and method of making same
04/01/2003US6541796 Opto-electronic device with self-aligned ohmic contact layer
04/01/2003US6541795 Thin film semiconductor device and production method for the same
04/01/2003US6541793 Active layer is a silicon film crystallized using a metal element; elimination of bad affection of such metal element to the thin film transistor characteristics using an n-type dopant; display device
04/01/2003US6541787 Optically aligning a loadport on a process machine by transmitting light through a system of apertures
04/01/2003US6541786 Plasma pinch high energy with debris collector
04/01/2003US6541784 Electron beam exposure system and exposing method using an electron beam
04/01/2003US6541783 Reticle having an apertured weakly scattering membrane with selective strongly scattering regions between the apertures; provides independent exposure dosage levels that can be mixed to provide a wide range of exposure levels with high contrast
04/01/2003US6541781 Waveguide for microwave excitation of plasma in an ion beam guide
04/01/2003US6541780 Particle beam current monitoring technique
04/01/2003US6541776 Device for electrostatic deflection of a particle beam
04/01/2003US6541747 Focal mechanism and method for controlling focal point position, and apparatus and method for inspecting semiconductor wafer
04/01/2003US6541730 Method and apparatus for cutting a non-metal substrate by using a laser beam
04/01/2003US6541710 Method and apparatus of supporting circuit component having a solder column array using interspersed rigid columns
04/01/2003US6541709 Inherently robust repair process for thin film circuitry using uv laser
04/01/2003US6541702 Semiconductor device
04/01/2003US6541434 Cleaning solution for semiconductor surfaces following chemical-mechanical polishing
04/01/2003US6541406 Silicon nitride sintered material and process for production thereof
04/01/2003US6541405 Reducing in radiation transmission variations; optics, lenses; oxidation decomposition of organosilicon compound
04/01/2003US6541401 Wafer pretreatment to decrease rate of silicon dioxide deposition on silicon nitride compared to silicon substrate
04/01/2003US6541400 Process for CVD deposition of fluorinated silicon glass layer on semiconductor wafer
04/01/2003US6541399 SABPSG process real temperature monitor
04/01/2003US6541398 Ultralow dielectric constant material as an intralevel or interlevel dielectric in a semiconductor device and electronic device containing the same
04/01/2003US6541397 Removable amorphous carbon CMP stop
04/01/2003US6541396 Method of manufacturing a semiconductor device using a low dielectric constant organic film grown in a vacuum above an inlaid interconnection layer