Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
03/2003
03/27/2003WO2003024877A1 Method and device for contactless handling or fixing of a glass object
03/27/2003WO2003024871A1 Method for preparing a stable lead zircon-titanate sol and method for preparing films based on same
03/27/2003WO2003024869A1 Electronic device comprising a mesoporous silica layer and composition for preparing the mesoporous silica layer
03/27/2003WO2003024865A2 Method for producing micro-electromechanical components
03/27/2003WO2003024711A2 Method for producing a ceramic substrate and ceramic substrate
03/27/2003WO2003024673A1 Robot hand with positioning function for semiconductor wafer and liquid crystal glass substrate
03/27/2003WO2003024653A1 Method for the production of a soldered connection
03/27/2003WO2003024630A1 Method and apparatus for cleaning substrates using liquid carbon dioxide
03/27/2003WO2003024620A1 Electro-optical component including a fluorinated poly (phenylene ether ketone) protective coating and related methods
03/27/2003WO2003024186A2 Methods and apparatus for patterning a surface
03/27/2003WO2003009341A3 Damascene structure with integral etch stop layer
03/27/2003WO2003008304A9 Protective shipper
03/27/2003WO2003007368A3 Method of forming nitride capped cu lines with reduced electromigration along the cu/nitride interface
03/27/2003WO2003006705A3 Wafer fabrication buffer station
03/27/2003WO2003001603A3 Bipolar transistor with raised extrinsic base fabricated in an integrated bicmos circuit
03/27/2003WO2003001575A3 Preparation of graded semiconductor films by the layer-by-layer assembly of nanoparticles
03/27/2003WO2003000964B1 METHOD FOR PREPARING GaN BASED COMPOUND SEMICONDUCTOR CRYSTAL
03/27/2003WO2002097172A3 Molecular beam epitaxy equipment
03/27/2003WO2002091435A3 Device for wet cleaning disc-shaped substrates
03/27/2003WO2002089186A3 Deposition and skipe annealing of tungsten silicide films
03/27/2003WO2002082489A3 Ion source filament
03/27/2003WO2002080265A3 Plasma processor and method for operating same
03/27/2003WO2002077327B1 Mask plate design
03/27/2003WO2002075791A3 Metal gate stack with etch stop layer improved through implantation of metallic atoms
03/27/2003WO2002069387A3 Die attaching adhesive with a low curing temperature
03/27/2003WO2002059945A3 Oxidized film structure and method of making epitaxial metal oxide structure
03/27/2003WO2002054458A3 Method for the manufacture of micro structures
03/27/2003WO2002045147A3 Method for pretreating dielectric layers to enhance the adhesion of cvd metal layers thereto
03/27/2003WO2002037569A3 Trench gate mos semiconductor device
03/27/2003WO2002037130A3 Method for testing integrated circuits
03/27/2003WO2002033745A3 Method and apparatus for providing communication between a defect source identifier and a tool data collection and control system
03/27/2003WO2002025696A9 Reducing deposition of process residues on a surface in a chamber
03/27/2003WO2002024983A9 Integrated phase separator for ultra high vacuum system
03/27/2003WO2002024410A9 Cmp apparatus and methods to control the tilt of the carrier head, the retaining ring and the pad conditioner
03/27/2003WO2002023620A3 Connection for conducting high frequency signal between a circuit and a discrete electrical component
03/27/2003WO2002023231A3 Generation of a library of periodic grating diffraction signals
03/27/2003WO2002017030B1 Methods and apparatus for obtaining data for process operation, optimization, monitoring, and control
03/27/2003US20030061596 Exposure apparatus, method of controlling same, and method of manufacturing devices
03/27/2003US20030061595 Exposure method for correcting line width variation in a photomask
03/27/2003US20030061585 Design system of integrated circuit and its design method and program
03/27/2003US20030061578 Logic optimization device for automatically designing integrated circuits
03/27/2003US20030061573 Method and program for supporting register-transfer-level design of semiconductor integrated circuit
03/27/2003US20030061556 Semiconductor device and its design method
03/27/2003US20030061555 Semiconductor integrated circuit
03/27/2003US20030060985 Computer-implemented method of defect analysis
03/27/2003US20030060922 Method and apparatus for aligning a cassette
03/27/2003US20030060917 Substrate processing apparatus control system and substrate processing apparatus
03/27/2003US20030060916 Automatic production quality control method and system
03/27/2003US20030060183 Signal processing semiconductor integrated circuit device
03/27/2003US20030060177 Integrated circuit and receiving device
03/27/2003US20030060143 Chemical mechanical polishing apparatus with rotating belt
03/27/2003US20030060139 Method and apparatus for mechanical and chemical-mechanical planarization of microelectronic substrates with metal compound abrasives
03/27/2003US20030060138 Polishing pad for semiconductor wafer and polishing process using thereof
03/27/2003US20030060135 Rare earth salt/oxidizer-based cmp method
03/27/2003US20030060131 Method of cleaning a probe card
03/27/2003US20030060128 Apparatus and method for conditioning and monitoring media used for chemical-mechanical planarization
03/27/2003US20030060126 System and method of defect optimization for chemical mechanical planarization of polysilicon
03/27/2003US20030060066 Solder ball and interconnection structure using the same
03/27/2003US20030060064 Spiral contactor and manufacturing method for this apparatus, and a semiconductor inspecting equipment and electronical parts using this apparatus
03/27/2003US20030060059 Versatile plasma processing system for producing oxidation resistant barriers
03/27/2003US20030060058 Method and structure for oxide/silicon nitride interface substructure improvements
03/27/2003US20030060057 Method of forming ultrathin oxide layer
03/27/2003US20030060056 Etching solution for signal wire and method of fabricating thin film transistor array panel with the same
03/27/2003US20030060055 Resist pattern, a method for fabricating a resist pattern, a method for patterning a thin film and a method for manufacturing a micro device
03/27/2003US20030060054 Plasma treatment method
03/27/2003US20030060053 Method for manufacturing semiconductor device
03/27/2003US20030060052 Fabrication of 3-D capacitor with dual damascene process
03/27/2003US20030060050 Semiconductor wafer with improved local flatness, and method for its production
03/27/2003US20030060049 Processes for chemical-mechanical polishing of a semiconductor wafer
03/27/2003US20030060048 Chemically enhanced focused ion beam micro-machining of copper
03/27/2003US20030060047 Methods and apparatuses for monitoring and controlling mechanical or chemical-mechanical planarization of microelectronic substrate assemblies
03/27/2003US20030060046 Methods and apparatuses for monitoring and controlling mechanical or chemical-mechanical planarization of microelectronic substrate assemblies
03/27/2003US20030060044 Liquid phase growth method and liquid phase growth apparatus
03/27/2003US20030060043 Hardening flux, soldering resist, semiconductor package reinforced by hardening flux, semiconductor device and method of producing semiconductor package and semiconductor device
03/27/2003US20030060042 Semiconductor device having barrier layer between ruthenium layer and metal layer and method for manufacturing the same
03/27/2003US20030060041 Dual-stack, ball-limiting metallurgy and method of making same
03/27/2003US20030060040 Method of electroless plating copper on nitride barrier
03/27/2003US20030060039 Method of passivating an oxide surface subjected to a conductive material anneal
03/27/2003US20030060038 Forming interconnects
03/27/2003US20030060037 Method of manufacturing trench conductor line
03/27/2003US20030060036 Method of fabricating copper interconnects with very low-k inter-level insulator
03/27/2003US20030060035 Semiconductor device
03/27/2003US20030060034 Method of transferring ultra-thin substrates and application of the method to the manufacture of a multi-layer thin film device
03/27/2003US20030060033 Transistor with highly uniform threshold voltage
03/27/2003US20030060032 Microelectronic unit forming methods and materials
03/27/2003US20030060031 Manufacturing method of schottky barrier diode
03/27/2003US20030060030 Method for processing a wafer and apparatus for performing the same
03/27/2003US20030060029 Method for forming a diffusion region
03/27/2003US20030060028 Method for forming an interface free layer of silicon on a substrate of monocrystalline silicon
03/27/2003US20030060027 Method for manufacturing a semiconductor device
03/27/2003US20030060026 Laser annealing method and apparatus
03/27/2003US20030060025 Techniques for maintaining alignment of cut dies during substrate dicing
03/27/2003US20030060024 Method of manufacturing semiconductor device
03/27/2003US20030060023 Manufacturing method for semiconductor apparatus
03/27/2003US20030060022 Method for cutting semiconductor wafers
03/27/2003US20030060021 Method of and mechanism for peeling adhesive tape bonded to segmented semiconductor wafer
03/27/2003US20030060020 Method and apparatus for finishing substrates for wafer to wafer bonding
03/27/2003US20030060019 Process of increasing screen dielectric thickness
03/27/2003US20030060018 Metal gate CMOS and method of manufacturing the same
03/27/2003US20030060017 Method of manufacturing capacitor
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