Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
04/2003
04/22/2003US6552263 Method of injection molded flip chip encapsulation
04/22/2003US6552143 Polymeric compound and resin composition for photoresist
04/22/2003US6551972 For effectively removing contaminants such as organics, dust and metals from surfaces
04/22/2003US6551949 Vapor deposition; overcoating semiconductor substrate
04/22/2003US6551948 Flash memory device and a fabrication process thereof, method of forming a dielectric film
04/22/2003US6551947 Method of forming a high quality gate oxide at low temperatures
04/22/2003US6551946 Two-step oxidation process for oxidizing a silicon substrate wherein the first step is carried out at a temperature below the viscoelastic temperature of silicon dioxide and the second step is carried out at a temperature above the viscoelastic temperature
04/22/2003US6551945 Process for manufacturing a semiconductor device
04/22/2003US6551944 Process for manufacturing a semiconductor material wafer comprising single-Crystal regions separated by insulating material regions
04/22/2003US6551943 Wet clean of organic silicate glass films
04/22/2003US6551942 Methods for etching tungsten stack structures
04/22/2003US6551941 Providing an etch stack; etching using plasma to form a first passivation layer on sidewalls of silicon-containing gate layer; etching the remaining portion of silicon-containing gate layer using a plasma generated from a second source gas
04/22/2003US6551940 Undoped silicon dioxide as etch mask for patterning of doped silicon dioxide
04/22/2003US6551939 Plasma surface treatment method and resulting device
04/22/2003US6551938 N2/H2 chemistry for dry development in top surface imaging technology
04/22/2003US6551937 Process for device using partial SOI
04/22/2003US6551936 Method of etching patterns into epitaxial material
04/22/2003US6551935 Useful in chemical-mechanical polishing or chemical mechanical procedures
04/22/2003US6551934 Process for fabricating semiconductor device and apparatus for fabricating semiconductor device
04/22/2003US6551932 Method for forming metal line in a semiconductor device
04/22/2003US6551931 Method to selectively cap interconnects with indium or tin bronzes and/or oxides thereof and the interconnect so capped
04/22/2003US6551930 Etching an organic material layer, particularly for producing interconnections of the damascene type
04/22/2003US6551929 Bifurcated deposition process for depositing refractory metal layers employing atomic layer deposition and chemical vapor deposition techniques
04/22/2003US6551928 Method of forming a semiconductor device with a multi-layer WSix film with small grain size structure
04/22/2003US6551927 CoSix process to improve junction leakage
04/22/2003US6551926 Electron beam annealing of metals, alloys, nitrides and silicides
04/22/2003US6551925 Method of forming a trench isolation structure resistant to hot phosphoric acid by extending trench liner to shoulder portions
04/22/2003US6551924 Post metalization chem-mech polishing dielectric etch
04/22/2003US6551923 Dual width contact for charge gain reduction
04/22/2003US6551922 Method for making a semiconductor device by variable chemical mechanical polish downforce
04/22/2003US6551921 Method of polishing a stack of dielectric layers including a fluorine containing silicon oxide layer
04/22/2003US6551920 Semiconductor device and fabrication method thereof
04/22/2003US6551919 Method for forming a dual inlaid copper interconnect structure
04/22/2003US6551918 Semiconductor device and method of fabrication thereof, circuit board, and electronic equipment
04/22/2003US6551917 Method of locating conductive spheres utilizing screen and hopper of solder balls
04/22/2003US6551915 Thermal annealing/hydrogen containing plasma method for forming structurally stable low contact resistance damascene conductor structure
04/22/2003US6551914 Method of forming polish stop by plasma treatment for interconnection
04/22/2003US6551913 Method for fabricating a gate electrode of a semiconductor device
04/22/2003US6551912 Method of forming a conductive coating on a semiconductor device
04/22/2003US6551911 Method for producing Schottky diodes and Schottky diodes
04/22/2003US6551910 Method of manufacturing solid-state image pickup device
04/22/2003US6551909 Semiconductor device with alternating conductivity type layer and method of manufacturing the same
04/22/2003US6551907 Metal-gettering method used in the manufacture of crystalline-Si TFT
04/22/2003US6551906 Method of fabricating semiconductor device
04/22/2003US6551905 Wafer adhesive for semiconductor dry etch applications
04/22/2003US6551904 Method of manufacturing photodiodes
04/22/2003US6551903 Melt through contact formation method
04/22/2003US6551902 Process for fabricating a buried, laterally insulated zone of increased conductivity in a semiconductor substrate
04/22/2003US6551901 Method for preventing borderless contact to well leakage
04/22/2003US6551900 Trench gate oxide formation method
04/22/2003US6551899 Methods of fabricating memory cells for nonvolatile memory devices
04/22/2003US6551898 Creation of a polarizable layer in the buried oxide of silicon-on-insulator substrates for the fabrication of non-volatile memory
04/22/2003US6551897 Wafer trench article and process
04/22/2003US6551896 Capacitor for analog circuit, and manufacturing method thereof
04/22/2003US6551895 Metal oxide semiconductor capacitor utilizing dummy lithographic patterns
04/22/2003US6551894 Stacked capacitor-type semiconductor storage device and manufacturing method thereof
04/22/2003US6551893 Atomic layer deposition of capacitor dielectric
04/22/2003US6551891 Process for fabricating a self-aligned vertical bipolar transistor
04/22/2003US6551890 Method of manufacturing a semiconductor device comprising a bipolar transistor and a capacitor
04/22/2003US6551889 Method of producing a SI-GE base heterojunction bipolar device
04/22/2003US6551888 Tuning absorption levels during laser thermal annealing
04/22/2003US6551887 Method of forming a spacer
04/22/2003US6551886 Ultra-thin body SOI MOSFET and gate-last fabrication method
04/22/2003US6551885 Low temperature process for a thin film transistor
04/22/2003US6551884 Semiconductor device including gate insulation films having different thicknesses
04/22/2003US6551883 MOS device with dual gate insulators and method of forming the same
04/22/2003US6551882 Semiconductor device manufacturing method permitting suppression of leak current through the PN junction
04/22/2003US6551881 Self-aligned dual-oxide umosfet device and a method of fabricating same
04/22/2003US6551880 Method of utilizing fabrication process of floating gate spacer to build twin-bit monos/sonos memory
04/22/2003US6551879 Method for forming an oxide layer on a nitride layer
04/22/2003US6551878 Mini flash process and circuit
04/22/2003US6551877 Method of manufacturing memory device
04/22/2003US6551876 Processing methods of forming an electrically conductive plug to a node location
04/22/2003US6551875 Method of forming a uniform collar oxide layer over an upper portion of a sidewall of a trench extending into a semiconductor substrate
04/22/2003US6551874 Self-aligned STI process using nitride hard mask
04/22/2003US6551873 Method for forming a tantalum oxide capacitor
04/22/2003US6551872 Method for making integrated circuit including interconnects with enhanced electromigration resistance using doped seed layer and integrated circuits produced thereby
04/22/2003US6551871 Process of manufacturing a dual gate CMOS transistor
04/22/2003US6551870 Method of fabricating ultra shallow junction CMOS transistors with nitride disposable spacer
04/22/2003US6551869 Lateral PNP and method of manufacture
04/22/2003US6551868 Vertical power component manufacturing method
04/22/2003US6551867 Non-volatile semiconductor memory device and method for manufacturing the same
04/22/2003US6551866 Method of manufacturing a semiconductor memory device
04/22/2003US6551863 Flip chip dip coating encapsulant
04/22/2003US6551862 Semiconductor device and method of manufacturing the same
04/22/2003US6551861 Method of making a semiconductor chip assembly by joining the chip to a support circuit with an adhesive
04/22/2003US6551859 Chip scale and land grid array semiconductor packages
04/22/2003US6551858 Method of producing a semiconductor device having two semiconductor chips sealed by a resin
04/22/2003US6551857 Three dimensional structure integrated circuits
04/22/2003US6551856 Method for forming copper pad redistribution and device formed
04/22/2003US6551855 Substrate strip and manufacturing method thereof
04/22/2003US6551854 Semiconductor device having bump electrodes and method of manufacturing the same
04/22/2003US6551852 Method of forming a recessed magnetic storage element
04/22/2003US6551851 Production of diaphragms over a cavity by grinding to reduce wafer thickness
04/22/2003US6551848 Method for fabricating semiconductor light emitting device
04/22/2003US6551847 Inspection analyzing apparatus and semiconductor device
04/22/2003US6551845 Method of temporarily securing a die to a burn-in carrier
04/22/2003US6551817 Generating chips; form microarray on subtrate, separate into chips mate chips to a package
04/22/2003US6551811 Protein comprises at least one site for N-linked glycosylation and is attached to a plasma membrane by a glycosylphosphatidylinositol radical
04/22/2003US6551765 Coating apparatus, discharge device, and coating method
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