Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
04/2003
04/17/2003WO2003021655A3 Method of cleaning an inter-level dielectric interconnect
04/17/2003WO2003021640A3 Method for semiconductor gate doping
04/17/2003WO2003012548A3 System for measuring an optical system, especially an objective
04/17/2003WO2003008301A8 300mm single stackable film frame carrier
04/17/2003WO2003007383A3 Algan/gan hemts having a gate contact on a gan based cap segment and methods of fabricating same
04/17/2003WO2002097173A3 Semi-insulating silicon carbide without vanadium domination
04/17/2003WO2002080231A3 Semiconductor wafer lifting device and methods for implementing the same
04/17/2003WO2002080229A3 Microelectronic assembly with die support and method
04/17/2003WO2002076511A3 Plasma surface treatment method and device for carrying out said method
04/17/2003WO2002075011A3 Thin film forming method and apparatus
04/17/2003WO2002073318A3 Method and device for vibration control
04/17/2003WO2002067319A3 Copper interconnect structure having diffusion barrier
04/17/2003WO2002067300A3 Singulation apparatus and method for manufacturing semiconductors
04/17/2003WO2002067298A3 Consecutive deposition system
04/17/2003WO2002059962A3 Viscous protective overlayers for planarization of integrated circuits
04/17/2003WO2002058159A9 Mos-gated power device with doped polysilicon body and process for forming same
04/17/2003WO2002056343A3 Methods for improved planarization post cmp processing
04/17/2003WO2002056338A3 Device for the plasma-mediated working of surfaces on planar substrates
04/17/2003WO2002050895A3 Controlled anneal conductors for integrated circuit interconnects
04/17/2003WO2002049107A3 Method for stacking semiconductor die within an implanted medical device
04/17/2003WO2002047172A9 A high frequency interconnect system using micromachined plugs and sockets
04/17/2003WO2002046864A9 Automated wafer handling with graphic user interface
04/17/2003WO2002043159A3 Doped semiconductor nanocrystals
04/17/2003WO2002041366A3 Nitrogen implantation using a shadow effect to control gate oxide thickness in sti dram semiconductors
04/17/2003WO2002037183A3 Inverse resist coating process
04/17/2003WO2002029390A3 Method and apparatus to provide for automated process verification and hierarchical substrate examination
04/17/2003WO2002025697A3 Apparatus for etching semiconductor samples and a source for providing a gas by sublimation thereto
04/17/2003WO2001099155A3 Nitride semiconductor substrate and method for manufacturing the same, and nitride semiconductor device using nitride semiconductor substrate
04/17/2003WO2001073868A3 Device enclosures and devices with integrated battery
04/17/2003WO2000002233A3 Simplified process for producing nanoporous silica
04/17/2003WO1999060829A3 Method and apparatus for making electrical traces, circuits and devices
04/17/2003US20030074646 Mask pattern generating method and manufacturing method of semiconductor apparatus
04/17/2003US20030074641 Latch-up verifying method and latch-up verifying apparatus capable of varying over-sized region
04/17/2003US20030074639 Method for automatically correcting overlay alignment of a semiconductor wafer
04/17/2003US20030074618 Dual mode ASIC BIST controller
04/17/2003US20030074615 Weighted random pattern test using pre-stored weights
04/17/2003US20030074168 Method for determining statistical fluctuations of values of geometrical properties of structures required for the fabrication of semiconductor components
04/17/2003US20030074156 Graphic contour extracting method, pattern inspecting method, program and pattern inspection system
04/17/2003US20030074098 Integrated equipment set for forming an interconnect on a substrate
04/17/2003US20030074097 Lithography; stacked containers
04/17/2003US20030073860 Vapor deposition of an organometallic compound; forming silicide
04/17/2003US20030073795 Transparent to ultraviolet radiation; pattern clarity
04/17/2003US20030073601 Mixture containing nonionic surfactant, amine and adhesion agent
04/17/2003US20030073593 Slurry for mechanical polishing (CMP) of metals and use thereof
04/17/2003US20030073390 Methods and apparatuses for mechanical and chemical-mechanical planarization of microelectronic-device substrate assemblies of planarizing pads
04/17/2003US20030073389 Methods and apparatuses for mechanical and chemical-mechanical planarization of microelectronic-device substrate assemblies on planarizing pads
04/17/2003US20030073388 Methods and apparatuses for mechanical and chemical-mechanical planarization of microelectronic-device substrate assemblies on planarizing pads
04/17/2003US20030073387 Methods and apparatuses for mechanical and chemical-mechanical planarization of microelectronic-device substrate assemblies on planarizing pads
04/17/2003US20030073386 Chemical mechanical polishing compositions for metal and associated materials and method of using same
04/17/2003US20030073385 Self-cleaning colloidal slurry composition and process for finishing a surface of a substrate
04/17/2003US20030073383 Polishing platen of chemical mechanical polishing apparatus and planarization method using the same
04/17/2003US20030073381 Workpiece carrier with adjustable pressure zones and barriers
04/17/2003US20030073323 Multi-chamber system having compact installation set-up for an etching facility for semiconductor device manufacturing
04/17/2003US20030073322 Ashing apparatus, ashing methods, and methods for manufacturing semiconductor devices
04/17/2003US20030073321 Etch process for dielectric materials comprising oxidized organo silane materials
04/17/2003US20030073320 Method for preventing surface corrosion in an edge bead removal process
04/17/2003US20030073318 Atomic layer doping apparatus and method
04/17/2003US20030073317 Method of manufacturing a semiconductor device and a semiconductor device
04/17/2003US20030073316 Novel post etching treatment process for high density oxide etcher
04/17/2003US20030073315 Method of manufacturing crystal of III-V compounds of the nitride system, crystal substrate of III-V compounds of the nitride system, crystal film of III-V compounds of the nitride system, and method of manufacturing device
04/17/2003US20030073314 GCIB processing to improve interconnection vias and improved interconnection via
04/17/2003US20030073313 Low leakage power transistor and method of forming
04/17/2003US20030073312 Etching systems and processing gas specie modulation
04/17/2003US20030073311 For etching surfaces, such as copper and tantalum as would be applicable in the fabrication of integrated circuits
04/17/2003US20030073310 Planarization of metal layers on a semiconductor wafer through non-contact de-plating and control with endpoint detection
04/17/2003US20030073309 Apparatus and method for edge bead removal
04/17/2003US20030073308 Low selectivity deposition methods
04/17/2003US20030073307 Forming conductive layers on insulators by physical vapor deposition
04/17/2003US20030073306 Semiconductor processing methods of forming integrated circuitry, forming conductive lines, forming a conductive grid, forming a conductive network, forming an electrical interconnection to a node location, forming an electrical interconnection with a transistor source/drain region, and integrated circuitry
04/17/2003US20030073305 Method of forming a crystalline phase material
04/17/2003US20030073304 Selective tungsten stud as copper diffusion barrier to silicon contact
04/17/2003US20030073303 Method for forming multi-layer wiring structure
04/17/2003US20030073302 Methods for formation of air gap interconnects
04/17/2003US20030073301 Multilayered diffusion barrier structure for improving adhesion property
04/17/2003US20030073300 Method of forming a bump on a copper pad
04/17/2003US20030073299 Method of forming through-hole or recess in silicon substrate
04/17/2003US20030073298 Methods of forming DRAM assemblies, transistor devices, and openings in substrates
04/17/2003US20030073297 Method for fabricating a semiconductor structure using a protective layer, and semiconductor structure
04/17/2003US20030073296 A Method Of Forming At Least One Interconnection To A Source/Drain Region In Silicon-On-Insulator Integrated Circuitry
04/17/2003US20030073294 Depositing a component of film on a substrate at a first temperature; depositing a second component of film on substrate at a second temperature higher than first temperature; annealing to form strontium ruthenite film
04/17/2003US20030073293 In situ growth of oxide and silicon layers
04/17/2003US20030073291 Method of forming stacked gate for flash memories
04/17/2003US20030073290 Method for growing ultra thin nitrided oxide
04/17/2003US20030073289 Trench-gate semiconductor devices and their manufacture
04/17/2003US20030073288 Method of forming nitridated tunnel oxide barriers for flash memory technology circuitry and STI and LOCOS isolation
04/17/2003US20030073287 Semiconductor structure with improved smaller forward voltage loss and higher blocking capability
04/17/2003US20030073286 Novel MIM process for logic-based embedded RAM
04/17/2003US20030073285 Even nucleation between silicon and oxide surfaces for thin silicon nitride film growth
04/17/2003US20030073284 Even nucleation between silicon and oxide surfaces for thin silicon nitride film growth
04/17/2003US20030073283 Method for increasing the capacitance in a storage trench and trench capacitor having increased capacitance
04/17/2003US20030073282 Vertical/horizontal MIMCap method
04/17/2003US20030073281 Semiconductor memory device and manufacturing method thereof
04/17/2003US20030073280 Semiconductor device and fabrication process therefor
04/17/2003US20030073279 Compatible embedded DRAM process for MIM capacitor
04/17/2003US20030073278 Oxide film forming method
04/17/2003US20030073277 Structures comprising transistor gates
04/17/2003US20030073276 Method for manufacturing a self-aligned split-gate flash memory cell
04/17/2003US20030073275 Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bitline and vertical word line transistor, and a memory array made thereby
04/17/2003US20030073274 Compound semiconductor device and method for manufacturing the same
04/17/2003US20030073273 Semiconductor device and method of manufacturing the same
1 ... 4714 4715 4716 4717 4718 4719 4720 4721 4722 4723 4724 4725 4726 4727 4728 4729 4730 4731 4732 4733 4734 ... 6590