Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
05/2003
05/01/2003WO2003036702A2 Integrated circuit having interconnect to a substrate and method therefor
05/01/2003WO2003036701A1 Low-temperature post-dopant activation process
05/01/2003WO2003036700A1 Device and method for microwave plasma processing, and microwave power supply device
05/01/2003WO2003036699A2 Lateral semiconductor-on-insulator structure and corresponding manufacturing methods
05/01/2003WO2003036698A2 Method of depositing high-quality sige on sige substrates
05/01/2003WO2003036697A2 Methods of hyperdoping semiconductor materials and hyperdoped semiconductor materials and devices
05/01/2003WO2003036694A1 Thermal treatment equipment and thermal treatment method
05/01/2003WO2003036693A2 Method and system to provide electrical contacts for electrotreating processes
05/01/2003WO2003036692A2 Electronic assembly with filled no-flow underfill and methods of manufacture
05/01/2003WO2003036690A2 Identification code reader integrated with substrate carrier robot
05/01/2003WO2003036686A2 Method of patterning electrically conductive polymers
05/01/2003WO2003036685A2 Method and apparatus for applying conductive ink onto semiconductor substrates
05/01/2003WO2003036681A2 Methods and apparatus for plasma doping by anode pulsing
05/01/2003WO2003036680A1 Merie plasma reactor with showerhead rf electrode tuned to the plasma with arcing suppression
05/01/2003WO2003036679A2 Wafer pedestal tilt mechanism and cooling system
05/01/2003WO2003036388A1 Photosnesitive resin composition comprising quinonediazide sulfate ester compound
05/01/2003WO2003036387A2 Method of forming a pattern of sub-micron broad features
05/01/2003WO2003036377A1 A etchant for wires, a method for manufacturing the wires using the etchant, a thin film transistor array substrate and a method for manufacturing the same including the method
05/01/2003WO2003036376A1 A thin film transistor substrate of using insulating layers having low dielectric constant and a method of manufacturing the same
05/01/2003WO2003036374A1 Thin film transistor array panel for liquid crystal display and method for manufacturing the same
05/01/2003WO2003036309A1 Method and apparatus for electron density measurement
05/01/2003WO2003036308A1 Apparatus and method for handling and testing of wafers
05/01/2003WO2003036228A1 Balancing planarization of layers and the effect of underlying structure on the metrology signal
05/01/2003WO2003036227A1 Confocal wafer-inspection system and method
05/01/2003WO2003036224A1 Method and apparatus for wall film monitoring
05/01/2003WO2003035945A2 Substrate for epitaxy
05/01/2003WO2003035943A1 Electrolytic copper plating method, electrolytic copper plating-use phosphorus-containing copper anode and semiconductor wafer with little particles deposition plated by using them
05/01/2003WO2003035932A1 Method for forming a micro-pattern on a substrate by using capillary force
05/01/2003WO2003035927A2 Gas delivery apparatus for atomic layer deposition
05/01/2003WO2003035926A2 Improved precursors for chemical vapour deposition
05/01/2003WO2003035815A1 Composition for cleaning
05/01/2003WO2003035814A2 Improved post plasma ashing wafer cleaning formulation
05/01/2003WO2003035797A1 Aqueous cleaning composition containing copper-specific corrosion inhibitor for cleaning inorganic residues on semiconductor substrate
05/01/2003WO2003035782A1 Boron-containing polishing system and method
05/01/2003WO2003035763A1 Curable organopolysiloxane composition, use of the cured product of the composition, and semiconductor device
05/01/2003WO2003035720A1 Etch-stop resins
05/01/2003WO2003035541A2 Probe needle for testing semiconductor chips and method for producing said probe needle
05/01/2003WO2003035277A1 System for inverting substrate
05/01/2003WO2003021842A3 Hybrid circuit having nanotube electromechanical memory
05/01/2003WO2003011945A3 Siloxane resins
05/01/2003WO2003009388A3 Bipolar transistors and high electron mobility transistors
05/01/2003WO2003009376A3 Semiconductor structures and devices
05/01/2003WO2003007304A3 Magnetic memory unit and magnetic memory array
05/01/2003WO2003005438A3 Improved metal barrier behavior by sic:h deposition on porous materials
05/01/2003WO2003005414A3 Power mosfet with deep implanted junctions
05/01/2003WO2003001564A3 Semiconductor structure with a superlattice portion
05/01/2003WO2002103799A3 Method for producing a memory component
05/01/2003WO2002103772A3 Deep insulating trench and method for production thereof
05/01/2003WO2002101794A3 Variable method and apparatus for alignment of automated workpiece handling systems
05/01/2003WO2002097889A3 Semiconductor device and a method therefor
05/01/2003WO2002097876A3 Manufacture of trench-gate field-effect transistors
05/01/2003WO2002091460A3 Method of manufacturing an interconnection in an electoronic device
05/01/2003WO2002091432A3 Microelectronic structure comprising a hydrogen barrier layer
05/01/2003WO2002086580A3 Reflecting filter system in an illuminating device
05/01/2003WO2002084732A3 Method of manufacturing an electronic device
05/01/2003WO2002084705A3 Method for operating an mram semiconductor memory arrangement
05/01/2003WO2002080234A3 Method of plasma etching organic antireflective coating
05/01/2003WO2002075803A3 Ruthenium silicide processing methods
05/01/2003WO2002075793A3 System and method of providing mask defect printability analysis
05/01/2003WO2002071410A3 Higher program threshold voltage and faster programming rates based on improved erase methods
05/01/2003WO2002068712A3 Removal of etchant residues
05/01/2003WO2002065537A3 Formation of metal oxide gate dielectric
05/01/2003WO2002061821A3 Method of preparing indium phosphide heterojunction bipolar transistors
05/01/2003WO2002058153A3 Back illuminated imager with enhanced uv to near ir sensitivity
05/01/2003WO2002056358A9 Sidewalls as semiconductor etch stop and diffusion barrier
05/01/2003WO2002053322A3 System and method for polishing and planarization of semiconductor wafers using reduced surface area polishing pads
05/01/2003WO2002052288A3 Weighted random pattern test using pre-stored weights
05/01/2003WO2002049090A3 Method for polishing dielectric layers using fixed abrasive pads
05/01/2003WO2002045158A3 Memory cell with vertical floating gate transistor
05/01/2003WO2002044845A3 Protecting groups in polymers, photoresists and processes for microlithography
05/01/2003WO2002043116A3 Etching of high aspect ratio features in a substrate
05/01/2003WO2002041367A3 Self-aligned magnetic clad write line and method thereof
05/01/2003WO2002041355B1 Plasma processing comprising three rotational motions of an article being processed
05/01/2003WO2002038841A3 Atomic layer doping apparatus and method
05/01/2003WO2002037561A3 Dual gate oxide process for uniform oxide thickness
05/01/2003WO2002023625A8 Semiconductor device and fabrication method therefor
05/01/2003WO2002021574A3 Subframe method for displaying grey scales on an active matrix el device with subdivided msb subframe
05/01/2003WO2002015247A3 Method and apparatus for processing a semiconductor wafer using novel final polishing method
05/01/2003WO2002009175A3 Self-assembled electrical networks
05/01/2003US20030084418 Modification of integrated circuits
05/01/2003US20030084408 Semiconductor integrated circuit designing method and semiconductor device
05/01/2003US20030083776 Method and apparatus for aligning a cassette
05/01/2003US20030083766 System for selectively managing workpieces and a method for controlling the same
05/01/2003US20030083458 Method and apparatus of producing high-density polyidimide (HPI) film
05/01/2003US20030083392 Lower dielectric constant than corresponding non-porous matrix material, making porous matrix material particularly attractive for electronic applications including integrated circuits, multichip modules, and flat panel displays
05/01/2003US20030083215 Solvent mixture comprising water and an organic solvent, an amine compound, a transition metal-removing material
05/01/2003US20030083214 For cleaning after chemical mechanical polishing to remove copper oxide particles without corroding copper wiring or harming silicon dioxide layer; specified number of cleaning agents such as 2,2'-dipyridyl
05/01/2003US20030083203 Apparatus and methods for forming film pattern
05/01/2003US20030082998 Alkali metal-containing polishing system and method
05/01/2003US20030082927 Precursors for zirconium and hafnium oxide thin film deposition
05/01/2003US20030082926 Pattern formation method
05/01/2003US20030082925 Resin composition, heat-resistant resin paste and semiconductor device using them and method for manufacture thereof
05/01/2003US20030082924 Method of making a semiconductor device by converting a hydrophobic surface of a dielectric layer to a hydrophilic surface
05/01/2003US20030082923 Method and apparatus for radical oxidation of silicon
05/01/2003US20030082922 Method of fabricating integrated circuit having shallow junction
05/01/2003US20030082921 Method for eliminating particle source
05/01/2003US20030082920 Chamber-reversed dry etching
05/01/2003US20030082919 Method of detecting an endpoint during etching of a material within a recess
05/01/2003US20030082916 Method for reducing dimensions between patterns on a photoresist
05/01/2003US20030082915 Method of thinning semiconductor wafer capable of preventing its front from being contaminated and back grinding device for semiconductor wafers
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