Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
02/2007
02/22/2007WO2006052846A3 Programmable matrix array with chalcogenide material
02/22/2007WO2006047117A3 Method for reducing semiconductor die warpage
02/22/2007WO2006026422A3 Method and apparatus for etching material layers with high uniformity of a lateral etch rate across a substrate
02/22/2007WO2006007394A3 Strained tri-channel layer for semiconductor-based electronic devices
02/22/2007US20070044061 Semiconductor device, layout method and apparatus and program
02/22/2007US20070043230 Polishing slurries and methods for chemical mechanical polishing
02/22/2007US20070043124 Dispersion for chemical-mechanical polishing
02/22/2007US20070042693 Polishing pad and method of manufacture
02/22/2007US20070042682 Transparent polishing pad
02/22/2007US20070042612 Method for manufacturing semiconductor device
02/22/2007US20070042611 Method of producing a trench in a photo-resist on a III-V wafer and a compound wafer having a photo-resist including such a trench
02/22/2007US20070042610 Method of depositing low k barrier layers
02/22/2007US20070042609 Molecular caulk: a pore sealant for ultra-low k dielectrics
02/22/2007US20070042608 Method of substantially uniformly etching non-homogeneous substrates
02/22/2007US20070042607 Etch features with reduced line edge roughness
02/22/2007US20070042606 Creating novel structures using deep trenching of oriented silicon substrates
02/22/2007US20070042605 Method of etching a substrate and method of forming a feature on a substrate
02/22/2007US20070042604 Copolymers, polymer resin composition for buffer layer method of forming a pattern using the same and method of manufacturing a capacitor using the same
02/22/2007US20070042603 Method for etching having a controlled distribution of process results
02/22/2007US20070042602 Etch method using supercritical fluids
02/22/2007US20070042601 Method for etching high dielectric constant materials
02/22/2007US20070042600 Method for fabricating semiconductor device
02/22/2007US20070042599 Methods to facilitate etch uniformity and selectivity
02/22/2007US20070042598 Dielectric with sidewall passivating layer
02/22/2007US20070042597 Method for manufacturing semiconductor device
02/22/2007US20070042596 Method of forming an interconnect structure for a semiconductor device
02/22/2007US20070042595 Packaging of electronic chips with air-bridge structures
02/22/2007US20070042594 Semiconductor device and method of manufacturing the same
02/22/2007US20070042593 Bonding pad structure and method of forming the same
02/22/2007US20070042592 Novel approach to high temperature wafer processing
02/22/2007US20070042591 Signal routing on redistribution layer
02/22/2007US20070042590 Method for maufacturing semiconductor device
02/22/2007US20070042589 Composite inter-level dielectric structure for an integrated circuit
02/22/2007US20070042588 Single damascene with disposable stencil and method therefore
02/22/2007US20070042587 Method of forming a catalyst layer on the barrier layer of a conductive interconnect of a semiconductor device
02/22/2007US20070042586 STABILIZATION OF Ni MONOSILICIDE THIN FILMS IN CMOS DEVICES USING IMPLANTATION OF IONS BEFORE SILICIDATION
02/22/2007US20070042585 Method of forming metal plate pattern and circuit board
02/22/2007US20070042584 Method of forming a silicide
02/22/2007US20070042583 Semiconductor device and method of manufacturing the same
02/22/2007US20070042582 Method of forming a nanowire and method of manufacturing a semiconductor device using the same
02/22/2007US20070042581 Manufacturing method of semiconductor device and substrate processing apparatus
02/22/2007US20070042580 Ion implanted insulator material with reduced dielectric constant
02/22/2007US20070042579 System and method for ensuring migratability of circuits by masking portions of the circuits while improving performance of other portions of the circuits
02/22/2007US20070042578 Method for making junction and processed material formed using the same
02/22/2007US20070042577 Method of preparing a film layer-by-layer using plasma enhanced atomic layer deposition
02/22/2007US20070042575 Crystallization apparatus and method of amophous silicon
02/22/2007US20070042574 Method for manufacturing a semiconductor device
02/22/2007US20070042573 Methods of Forming Conductive Polysilicon Thin Films Via Atomic Layer Deposition and Methods of Manufacturing Semiconductor Devices Including Such Polysilicon Thin Films
02/22/2007US20070042572 Deposition of silicon germanium on silicon-on-insulator structures and bulk substrates
02/22/2007US20070042571 Method of forming group-III nitride crystal, layered structure and epitaxial substrate
02/22/2007US20070042570 Sequential deposition process for forming Si-containing films
02/22/2007US20070042569 Low temperature formation of patterned epitaxial Si containing films
02/22/2007US20070042568 Semiconductor device with a thinned semiconductor chip and method for producing the thinned semiconductor chip
02/22/2007US20070042567 Process for producing silicon wafer
02/22/2007US20070042566 Strained silicon on insulator (ssoi) structure with improved crystallinity in the strained silicon layer
02/22/2007US20070042565 Fluidic MEMS device
02/22/2007US20070042564 Semiconductor including STI and method for manufacturing the same
02/22/2007US20070042563 Single crystal based through the wafer connections technical field
02/22/2007US20070042562 Integrated circuit device
02/22/2007US20070042561 Semiconductor device and productioin method thereof
02/22/2007US20070042560 Method for growing thin nitride film onto substrate and thin nitride film device
02/22/2007US20070042559 Formation of nitrogen containing dielectric layers having a uniform nitrogen distribution therein using a high temperature chemical treatment
02/22/2007US20070042558 Process for manufacturing a high-quality SOI wafer
02/22/2007US20070042557 Data download to imager chip using image sensor as a receptor
02/22/2007US20070042556 Method of fabricating metal oxide semiconductor transistor
02/22/2007US20070042555 Formation of uniform silicate gate dielectrics
02/22/2007US20070042554 Methods of forming SRAM cells having landing pad in contact with upper and lower cell gate patterns
02/22/2007US20070042553 Fabrication method for semiconductor memory components
02/22/2007US20070042552 Method for fabricating a semiconductor device
02/22/2007US20070042551 Method of manufacturing a trench transistor having a heavy body region
02/22/2007US20070042550 Method for fabricating a semiconductor structure having selective dopant regions
02/22/2007US20070042549 Semiconductor device having reduced effective substrate resistivity and associated methods
02/22/2007US20070042548 Methods of forming floating gates in non-volatile memory devices including alternating layers of amorphous silicon and ALD dopant layers and floating gates so formed
02/22/2007US20070042547 Nonvolatile semiconductor memory device
02/22/2007US20070042546 Method for forming floating gates within NVM process
02/22/2007US20070042545 Bottom electrode for memory device and method of forming the same
02/22/2007US20070042544 Low-k spacer structure for flash memory
02/22/2007US20070042543 Method for manufacturing semiconductor device
02/22/2007US20070042542 Method for fabricating an interconnect arrangement with increased capacitive coupling and associated interconnect arrangement
02/22/2007US20070042541 Semiconductor device and its manufacture method
02/22/2007US20070042540 Method of forming a capacitor in a semiconductor device without wet etchant damage to the capacitor parts
02/22/2007US20070042539 Method of manufacturing a non-volatile memory device
02/22/2007US20070042538 Methods for preserving strained semiconductor substrate layers during cmos processing
02/22/2007US20070042537 Method of manufacturing a thin film transistor matrix substrate
02/22/2007US20070042536 Thin film transistor and method for manufacturing the same
02/22/2007US20070042535 Integrated circuit containing polysilicon gate transistors and fully silicidized metal gate transistors
02/22/2007US20070042534 Chip Package and Package Process Thereof
02/22/2007US20070042533 Heat conductive silicone grease composition and cured product thereof
02/22/2007US20070042532 System and methods for packing in turnkey services
02/22/2007US20070042531 Method for producing semiconductor device and semiconductor device
02/22/2007US20070042530 Electronic package for image sensor, and the packaging method thereof
02/22/2007US20070042529 Methods and apparatus for high-density chip connectivity
02/22/2007US20070042528 Defining electrode regions of electroluminescent panel
02/22/2007US20070042527 Microelectronic package optionally having differing cover and device thermal expansivities
02/22/2007US20070042526 Metal oxide solid solution, preparation and use thereof
02/22/2007US20070042524 MEMS devices having support structures with substantially vertical sidewalls and methods for fabricating the same
02/22/2007US20070042523 Photoelectric current multiplier using molecular crystal and production method therefor
02/22/2007US20070042522 Method of fabricating resistive probe having self-aligned metal shield
02/22/2007US20070042521 Microelectromechanical devices and fabrication methods
02/22/2007US20070042520 Method of manufacturing vertical GaN-based light emitting diode