Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
03/2007
03/01/2007WO2007023569A1 Nonvolatile semiconductor storage device and its write method
03/01/2007WO2007023557A1 Electronic component test apparatus and temperature control method in electronic component test apparatus
03/01/2007WO2007023551A1 Semiconductor integrated circuit and its fabrication method
03/01/2007WO2007023362A1 Doping of particulate semiconductor materials
03/01/2007WO2007023327A1 Magnetically alignable semiconductor chip and rewiring substrate and a method for magnetically aligning the semiconductor chip and the rewiring substrate
03/01/2007WO2007023239A1 Organometallic precursors for depositing a tantalum carbonitride or carbide film and method of depositing one such film
03/01/2007WO2007023011A2 Dual port gain cell with side and top gated read transistor
03/01/2007WO2007005228A9 Hermetic seals for micro-electromechanical system devices
03/01/2007WO2007002856A9 Software sequencer to dynamically adjust wafer transfer decision
03/01/2007WO2006138134A3 Junction leakage suppression in non-volatile memory devices by implanting phosphorous and arsenic into source and drain regions
03/01/2007WO2006136603B1 Method and device for the permanent connection of integrated circuit to a substrate
03/01/2007WO2006116432A3 Array source line in nand flash memory
03/01/2007WO2006113158A3 Mim capacitor and method of fabricating same
03/01/2007WO2006110645A3 Fluoride liquid cleaners with polar and non-polar solvent mixtures for cleaning low-k-containing microelectronic devices
03/01/2007WO2006107735A3 Method for making a semiconductor device including a superlattice with regions defining a semiconductor junction
03/01/2007WO2006104893A3 N+ polysilicon on high-k dielectric semiconductor devices
03/01/2007WO2006104886A3 Resilient probes for electrical testing
03/01/2007WO2006102292A3 Nanogaps: methods and devices containing same
03/01/2007WO2006102182A3 Process for electroless copper deposition
03/01/2007WO2006094290A9 Non-dispersive high density polysilicon capacitor utilizing amorphous silicon electrodes
03/01/2007WO2006073943A3 Method for forming a one mask hyperabrupt junction varactor using a compensated cathode contact
03/01/2007WO2006071552A3 Cleaning methods for silicon electrode assembly surface contamination removal
03/01/2007WO2006066211A3 Active and passive semiconductor device package
03/01/2007WO2006041633A3 Virtual ground memory array and method therefor
03/01/2007WO2006038976A3 Plasma processing system for treating a substrate
03/01/2007WO2006036992A3 System and method for active array temperature sensing and cooling
03/01/2007WO2006031452A3 Apparatus for the optimization of atmospheric plasma in a plasma processing system
03/01/2007WO2006023637A3 In situ surface contaminant removal for ion implanting
03/01/2007WO2006023044A3 Method of forming ultra shallow junctions
03/01/2007WO2006009818A3 Semiconductor structure processing using multiple laser beam spots
03/01/2007WO2005112090A3 Adhesion of a metal layer to a substrate and related structures
03/01/2007WO2005104226A8 Method for production of through-contacts in a plastic mass and semiconductor component with said through contacts
03/01/2007WO2005094398A3 Method and system for correcting a fault in a semiconductor manufacturing system
03/01/2007WO2005043196A3 Laser and detector device
03/01/2007US20070050741 Pattern verification method, program thereof, and manufacturing method of semiconductor device
03/01/2007US20070050093 Power supply system, power supply method and lot processing method
03/01/2007US20070050077 Chemical Mechanical Polishing Method and Apparatus
03/01/2007US20070050076 Method and apparatus for determining an operation status of a plasma processing apparatus, program and storage medium storing same
03/01/2007US20070049168 Polishing pad, pad dressing evaluation method, and polishing apparatus
03/01/2007US20070049166 Polishing method and polishing apparatus
03/01/2007US20070049056 Silicon surface preparation
03/01/2007US20070049055 Atomic layer deposition systems and methods including silicon-containing tantalum precursor compounds
03/01/2007US20070049054 Cobalt titanium oxide dielectric films
03/01/2007US20070049053 Pretreatment processes within a batch ALD reactor
03/01/2007US20070049052 Method for processing a layered stack in the production of a semiconductor device
03/01/2007US20070049051 Atomic layer deposition of Zrx Hfy Sn1-x-y O2 films as high k gate dielectrics
03/01/2007US20070049050 Bit line structure and method of fabrication
03/01/2007US20070049049 Test-key for checking interconnect and corresponding checking method
03/01/2007US20070049048 Method and apparatus for improving nitrogen profile during plasma nitridation
03/01/2007US20070049047 Porous thin-film-deposition substrate, electron emitting element, methods of producing them, and switching element and display element
03/01/2007US20070049046 Oxide film filled structure, oxide film filling method, semiconductor device and manufacturing method thereof
03/01/2007US20070049045 Atomic layer deposition method for depositing a layer
03/01/2007US20070049044 Porous organosilicate layers, and vapor deposition systems and methods for preparing same
03/01/2007US20070049043 Nitrogen profile engineering in HI-K nitridation for device performance enhancement and reliability improvement
03/01/2007US20070049042 Method of cleaning a wafer
03/01/2007US20070049041 Methods for etching doped oxides in the manufacture of microfeature devices
03/01/2007US20070049040 Multiple deposition for integration of spacers in pitch multiplication process
03/01/2007US20070049039 Method for fabricating a semiconductor device
03/01/2007US20070049038 Dry etching process to form a conductive layer within an opening without use of a mask during the formation of a semiconductor device
03/01/2007US20070049037 Methods of forming openings into dielectric material
03/01/2007US20070049036 Etching process for decreasing mask defect
03/01/2007US20070049035 Method of forming pitch multipled contacts
03/01/2007US20070049034 High aspect ratio gap fill application using high density plasma chemical vapor deposition
03/01/2007US20070049033 Film tray for fabricating flexible display
03/01/2007US20070049032 Protective coating for planarization
03/01/2007US20070049031 Etching method, method of fabricating metal film structure, and etching structure
03/01/2007US20070049030 Pitch multiplication spacers and methods of forming the same
03/01/2007US20070049029 Method of etching a TE/PCMO stack using an etch stop layer
03/01/2007US20070049028 Nanoimprint lithography template techniques for use during the fabrication of a semiconductor device and systems including same
03/01/2007US20070049027 Chemical mechanical polishing and method for manufacturing semiconductor device using the same
03/01/2007US20070049026 Dielectric film and process for its fabrication
03/01/2007US20070049025 Chemical-mechanical planarization composition having ketooxime compounds and associated method for use
03/01/2007US20070049024 Manufacture method for semiconductor device having concave portions filled with conductor containing Cu as its main composition
03/01/2007US20070049023 Zirconium-doped gadolinium oxide films
03/01/2007US20070049022 Nickel alloy silicide including indium and a method of manufacture therefor
03/01/2007US20070049021 Atomic layer deposition method
03/01/2007US20070049020 Method and apparatus for reducing tensile stress in a deposited layer
03/01/2007US20070049019 Method of selectively depositing materials on a substrate using a supercritical fluid
03/01/2007US20070049018 Method to reduce charge buildup during high aspect ratio contact etch
03/01/2007US20070049017 Plug fabricating method for dielectric layer
03/01/2007US20070049016 Microfeature workpieces and methods for forming interconnects in microfeature workpieces
03/01/2007US20070049015 Silicided recessed silicon
03/01/2007US20070049014 Method of performing salicide processes on MOS transistors
03/01/2007US20070049013 Method and apparatus for manufacturing semiconductor device, control program and computer storage medium
03/01/2007US20070049012 Dual damascene structure and fabrication thereof
03/01/2007US20070049011 Method of forming isolated features using pitch multiplication
03/01/2007US20070049010 Disposable pillars for contact formation
03/01/2007US20070049009 Method of manufacturing conductive layer
03/01/2007US20070049008 Method for forming a capping layer on a semiconductor device
03/01/2007US20070049007 Interconnect structure and method for forming the same
03/01/2007US20070049006 Method for integration of a low-k pre-metal dielectric
03/01/2007US20070049005 Method for forming dual damascene pattern in semiconductor manufacturing process
03/01/2007US20070049004 Semiconductor constructions, and methods of forming layers
03/01/2007US20070049003 Semiconductor constructions and methods of forming layers
03/01/2007US20070049002 Semiconductor device and method of packaging the same
03/01/2007US20070049001 Bumping process and structure thereof
03/01/2007US20070049000 Method for re-forming BGA of a semiconductor package
03/01/2007US20070048999 Method for fabricating semiconductor component having conductors and bonding pads with wire bondable surfaces and selected thickness
03/01/2007US20070048998 Method for fabricating semiconductor components encapsulated, bonded, interconnect contacts on redistribution contacts
03/01/2007US20070048997 Chip package structure and method for manufacturing bumps
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