H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
12/2011
12/22/2011	US20110309474 Trench capacitor
12/22/2011	US20110309473 Chip package with die and substrate
12/22/2011	US20110309471 Transistor structure with a sidewall-defined intrinsic base to extrinsic base link-up region and method of forming the structure
12/22/2011	US20110309470 Trench MOS Barrier Schottky Rectifier With A Planar Surface Using CMP Techniques
12/22/2011	US20110309469 Trench MOS Barrier Schottky Rectifier With A Planar Surface Using CMP Techniques
12/22/2011	US20110309468 Semiconductor chip package and method of manufacturing the same
12/22/2011	US20110309467 Semiconductor device and manufacturing method thereof
12/22/2011	US20110309466 Semiconductor device and method for manufacturing the same
12/22/2011	US20110309465 Seal ring structure in semiconductor devices
12/22/2011	US20110309463 Electrocaloric effect materials and thermal diodes
12/22/2011	US20110309458 A sensor and method for fabricating the same
12/22/2011	US20110309457 Method for Forming a Notched Gate Insulator for Advanced MIS Semiconductor Devices and Devices Thus Obtained
12/22/2011	US20110309455 Gate-Last Fabrication of Quarter-Gap MGHK FET
12/22/2011	US20110309452 Methods of manufacturing semiconductor devices
12/22/2011	US20110309451 Manufacturing method of semiconductor device and semiconductor device
12/22/2011	US20110309450 Semiconductor structure and method of fabrication thereof with mixed metal types
12/22/2011	US20110309449 Interface-free metal gate stack
12/22/2011	US20110309448 Differentially recessed contacts for multi-gate transistor of sram cell
12/22/2011	US20110309447 Transistor with threshold voltage set notch and method of fabrication thereof
12/22/2011	US20110309446 Strained thin body cmos device having vertically raised source/drain stressors with single spacer
12/22/2011	US20110309445 Semiconductor fabrication
12/22/2011	US20110309443 Method for controlling impurity density distribution in semiconductor device and semiconductor device made thereby
12/22/2011	US20110309442 Laterally double diffused metal oxide semiconductor transistor having a reduced surface field structure and method therefor
12/22/2011	US20110309441 Integrated semiconductor device having an insulating structure and a manufacturing method
12/22/2011	US20110309440 High voltage transistor using diluted drain
12/22/2011	US20110309439 Semiconductor device and method for manufacturing the same
12/22/2011	US20110309438 Semiconductor apparatus and manufacturing method thereof
12/22/2011	US20110309437 Semiconductor device
12/22/2011	US20110309435 Buried gate semiconductor device and method of manufacturing the same
12/22/2011	US20110309434 Nonvolatile memory device and manufacturing method thereof
12/22/2011	US20110309433 Semiconductor Device With Resistor Pattern And Method Of Fabricating The Same
12/22/2011	US20110309432 Nonvolatile semiconductor memory device and method for manufacturing the same
12/22/2011	US20110309431 Nonvolatile semiconductor memory device and method for manufacturing same
12/22/2011	US20110309430 Non-Volatile Memory With Flat Cell Structures And Air Gap Isolation
12/22/2011	US20110309429 Nonvolatile semiconductor memory device and manufacturing method thereof
12/22/2011	US20110309428 Semiconductor device
12/22/2011	US20110309426 Metal Control Gate Structures And Air Gap Isolation In Non-Volatile Memory
12/22/2011	US20110309425 Air Gap Isolation In Non-Volatile Memory
12/22/2011	US20110309424 Structure of memory device and process for fabricting the same
12/22/2011	US20110309423 Semiconductor device having a trench gate and method for manufacturing
12/22/2011	US20110309416 Structure and method to reduce fringe capacitance in semiconductor devices
12/22/2011	US20110309415 Sensor using ferroelectric field-effect transistor
12/22/2011	US20110309414 Diode polarity for diode array
12/22/2011	US20110309412 Superjunction collectors for transistors & semiconductor devices
12/22/2011	US20110309408 Semiconductor device and method of producing same
12/22/2011	US20110309400 Nitride semiconductor device and manufacturing method of the device
12/22/2011	US20110309380 Mother substrate, array substrate and method for manufacturing the same
12/22/2011	US20110309376 Method of cleaning silicon carbide semiconductor, silicon carbide semiconductor, and silicon carbide semiconductor device
12/22/2011	US20110309372 Enhancement-mode hfet circuit arrangement having high power and a high threshold voltage
12/22/2011	US20110309371 Schottky diode structure and method for fabricating the same
12/22/2011	US20110309370 Systems and methods for the crystallization of thin films
12/22/2011	US20110309364 Semiconductor display device
12/22/2011	US20110309362 Flat panel display apparatus and method of manufacturing the same
12/22/2011	US20110309360 Process for forming an electroactive layer
12/22/2011	US20110309356 Method for forming semiconductor film, method for forming semiconductor device and semiconductor device
12/22/2011	US20110309354 Large-scale Fabrication of Vertically Aligned ZnO Nanowire Arrays
12/22/2011	US20110309353 Semiconductor device and method for manufacturing the same
12/22/2011	US20110309334 Graphene/Nanostructure FET with Self-Aligned Contact and Gate
12/22/2011	US20110309333 Semiconductor devices fabricated by doped material layer as dopant source
12/22/2011	US20110309332 Epitaxial source/drain contacts self-aligned to gates for deposited fet channels
12/22/2011	US20110309324 Solid state devices with semi-polar facets and associated methods of manufacturing
12/22/2011	US20110309323 Method of manufacturing nano device by arbitrarily printing nanowire devices thereon and intermediate building block useful for the method
12/22/2011	US20110309322 Resistance change memory device with three-dimensional structure, and device array, electronic product and manufacturing method therefor
12/22/2011	US20110309321 Memristors with a switching layer comprising a composite of multiple phases
12/22/2011	US20110309319 Horizontally oriented and vertically stacked memory cells
12/22/2011	US20110309306 Fabrication of Silicon Nanowires
12/22/2011	US20110309152 Plastic card package and plastic card package manufacturing method
12/22/2011	US20110308737 Treatment of synthetic quartz glass substrate
12/22/2011	US20110308615 Crystal silicon processes and products
12/22/2011	US20110308603 Method for passivating a silicon surface
12/22/2011	US20110308598 Solution processing method for forming electrical contacts of organic devices
12/22/2011	US20110308597 Thick-film pastes containing lead-tellurium-lithium- oxides, and their use in the manufacture of semiconductor devices
12/22/2011	US20110308596 Thick-film pastes containing lead-tellurium-lithium-titanium-oxides, and their use in the manufacture of semiconductor devices
12/22/2011	US20110308595 Thick-film pastes containing lead- and tellurium-oxides, and their use in the manufacture of semiconductor devices
12/22/2011	US20110308593 Modified cadmium telluride layer, a method of modifying a cadmium telluride layer, and a thin film device having a cadmium telluride layer
12/22/2011	US20110308072 Open pattern inductor
12/22/2011	DE112004002747B4 Reaktive nanopartikuläre Cyclodextrinderivate als porenbildende Matrizen, diese enthaltende dielektrische Matrix und ultragering dielektrische Zusammensetzung, sowie unter deren Verwendung hergestellte gering und ultragering dielektrische Filme Reactive nanoparticulate cyclodextrin derivatives as pore-forming matrices containing these dielectric matrix and ultra low dielectric composition, as well as using them produced low and ultra-low dielectric films
12/22/2011	DE102011077764A1 Halbleitervorrichtung, die einen zellbereich und einen randbereich beinhaltet und eine struktur für hohe durchbruchspannung aufweist Semiconductor device, the cell region and a peripheral region includes and has a structure for a high breakdown voltage
12/22/2011	DE102011077504A1 Insulating member, metal base substrate, and semiconductor module, and manufacturing methods thereof Insulating member base metal substrates, and semiconductor modules, and manufacturing methods thereof
12/22/2011	DE102011002170A1 Elektronikbauelement-Package-Verriegelungssystem und Verfahren Electronic component package locking system and method
12/22/2011	DE102011001529A1 Plasmazerteilung und dadurch gebildete Halbleiterbauelemente Plasmazerteilung and semiconductor devices formed thereby
12/22/2011	DE102010030358A1 Verfahren zum Abtrennen einer Substratscheibe A method for separating a substrate wafer
12/22/2011	DE102010027703A1 Verfahren und Vorrichtung zum Entfernen eines reversibel angebrachten Vorrichtungswafers von einem Trägersubstrat A method and apparatus for removing a reversibly mounted device wafer from a carrier substrate
12/22/2011	DE102010024521A1 Verfahren zur Erhöhung der Transluzenz eines Substrats A method of increasing the translucency of a substrate
12/22/2011	DE102010024520A1 Method for increasing thermal mechanical resistance of ceramic substrate for mounting electrical components, involves covering edges of metallization layer by applying electrical isolation fill material between edges and substrate
12/22/2011	DE102010024498A1 Aufbau dreidimensionaler Bauteile mit nichtdiffundierenden Edel-oder Sondermetallen und deren Legierung durch Sputtertechnologie Construction of three-dimensional components with non-diffusing precious or special metals and their alloys by sputtering
12/22/2011	DE102010024307A1 Manufacturing method of metallic contact structure of e.g. metal wrap through solar cell, involves applying glass frit pastes to insulating layer on substrate, and making silver pastes to electrically contact substrate indirectly
12/22/2011	DE102010024040A1 Verfahren zur Politur einer Halbleiterscheibe Method for polishing a semiconductor wafer
12/22/2011	DE102010017497A1 Loading and/or unloading device for substrate processing equipment, has conveyor comprising centering device, where equipment exhibits control for movement of conveyor, centering device, elements, lifting and lowering device and array
12/22/2011	DE102010017483A1 Integrated lateral power circuit i.e. integrated power semiconductor component, for use in electronic control unit utilized in e.g. motor car for heating airbag, has trench extending from horizontal surface to insulation area
12/22/2011	DE102009051007B4 Verfahren zum Polieren einer Halbleiterscheibe A method of polishing a semiconductor wafer
12/22/2011	DE102008059648B4 Gateelektrodenstruktur mit großem ε, die nach der Transistorherstellung unter Anwendung eines Abstandshalters gebildet wird Gate electrode structure with large ε, which is formed after the transistor production using a spacer
12/22/2011	DE102008023054B4 Verfahren zur Herstellung einer epitaxierten Halbleiterscheibe A process for producing an epitaxially coated semiconductor wafer,
12/22/2011	DE102007045812B4 Verfahren zum Herstellen einer Speicherzelle, Speicherzelle sowie integrierte Schaltung A method for fabricating a memory cell, memory cell and integrated circuit
12/22/2011	DE102007017833B4 Halbleitervorrichtung und Verfahren zu ihrer Herstellung Semiconductor device and process for their preparation
12/22/2011	DE102006051489B4 Teststruktur für durch OPC-hervorgerufene Kurzschlüsse zwischen Leitungen in einem Halbleiterbauelement und Messverfahren Test structure for OPC caused by short-circuiting between lines in a semiconductor device and methods of measurement
12/22/2011	DE102006008454B4 Kontaktstellenstruktur, Kontaktstellen-Layoutstruktur, Halbleiterbauelement und Kontaktstellen-Layoutverfahren Pad structure, pads layout structure, semiconductor device and pads layout method
12/22/2011	DE102005063535B4 Verfahren zur Herstellung einer Halbleiteranordnung A process for producing a semiconductor device
12/22/2011	DE102005054177B4 Verfahren zum Herstellen einer Vielzahl von gehäusten Sensormodulen A method of manufacturing a plurality of sensor modules packaged
12/22/2011	DE102005038943B4 Verfahren zum Herstellen eines Feldeffekttransistors (FET) mit Leitungskanälen A method of manufacturing a field effect transistor (FET) with ducts

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