Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 8 - Arrangements for selecting an address in a digital store
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
08/2005
08/17/2005EP1563508A2 Electronic device with data storage device
08/17/2005EP1417672B1 Display device comprising an array of pixels allowing storage of data
08/17/2005CN1656566A Device for reducing the effects of leakage current within electronic devices
08/17/2005CN1655227A Image memory architecture for achieving high speed access
08/16/2005US6931500 Method for bus capacitance reduction
08/16/2005US6931483 Memory device having different burst order addressing for read and write operations
08/16/2005US6931482 Semiconductor memory device internally provided with logic circuit which can be readily controlled and controlling method thereof
08/16/2005US6931467 Memory integrated circuit device which samples data upon detection of a strobe signal
08/16/2005US6931462 Memory controller which increases bus bandwidth, data transmission method using the same, and computer system having the same
08/16/2005US6930955 Method and apparatus for establishing and maintaining desired read latency in high-speed DRAM
08/16/2005US6930951 Semiconductor memory device capable of accessing data in continuous burst mode regardless of location of accessed data
08/16/2005US6930929 Simultaneous read-write memory cell at the bit level for a graphics display
08/16/2005US6930927 Line selector for a matrix of memory elements
08/16/2005US6930923 Flash memory capable of utilizing one driving voltage output circuit to drive a plurality of word line drivers
08/16/2005US6930343 Nonvolatile memory device utilizing a vertical nanotube
08/11/2005US20050174878 Semiconductor memory module, memory system, circuit, semiconductor device, and DIMM
08/11/2005US20050174877 Bus arrangement and method thereof
08/11/2005US20050174874 High-frequency power amplifier module
08/11/2005US20050174873 Semiconductor memory device and method of operating same
08/11/2005US20050174862 Semiconductor memory device and method of testing semiconductor memory device
08/11/2005US20050174854 Memory device
08/11/2005US20050174840 Memory device
08/11/2005US20050174825 Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules
08/11/2005US20050174356 Decoder system capable of performing a plural-stage process
08/11/2005US20050174164 Integrated semiconductor memory with temperature-dependent voltage generation
08/11/2005US20050174160 Phase multiplier circuit
08/11/2005US20050174144 Look-up table
08/11/2005DE102004006769B3 Auslesevorrichtung Readout device
08/10/2005CN1652256A Memory device of memory for regulating reading voltage
08/10/2005CN1652255A Semiconductor memory device and method of testing semiconductor memory device
08/10/2005CN1652250A Redundancy relieving circuit
08/10/2005CN1652248A Method and memory system in which operating mode is set using address signal
08/10/2005CN1652098A Bus arrangement and method thereof
08/10/2005CN1214397C DDR SDRAM and SDRAM shared module with double data transmission rate
08/10/2005CN1214395C Memory address generator circuit and semiconductor memory device
08/09/2005US6928530 Method and device for sequential readout of a memory with address jump
08/09/2005US6928135 Shift register for pulse-cut clock signal
08/09/2005US6928027 Virtual dual-port synchronous RAM architecture
08/09/2005US6928026 Synchronous global controller for enhanced pipelining
08/09/2005US6928023 Apparatus for and method of controlling AIVC through block selection information in semiconductor memory device
08/09/2005US6928013 Timing control method for operating synchronous memory
08/09/2005US6928000 Semiconductor memory device having a resistance adjustment unit
08/09/2005US6927466 Magnetoresistive memory or sensor devices having improved switching properties and method of fabrication
08/09/2005US6927443 Nonvolatile semiconductor memory device
08/04/2005WO2005071529A2 Memory card that supports file system interoperability
08/04/2005US20050169097 Method and apparatus for coordinating memory operations among diversely-located memory components
08/04/2005US20050169096 PAA- based etchant, methods of using same, and resultant structures
08/04/2005US20050169095 Bit line discharge control method and circuit for a semiconductor memory
08/04/2005US20050169093 Phase-change memory device and method of writing a phase-change memory device
08/04/2005US20050169091 Semiconductor memory device suitable for mounting on portable terminal
08/04/2005US20050169090 Method for making high performance semiconductor memory devices
08/04/2005US20050169062 Data storage apparatus, data storage control apparatus, data storage control method, and data storage control program
08/04/2005US20050169061 Multi-port memory device for buffering between hosts and non-volatile memory devices
08/04/2005US20050169038 Semiconductor memory device
08/04/2005DE10361496A1 Anordnung mit einer Speichereinrichtung und einer programmgesteuerten Einheit Arrangement with a memory device and a programmable unit
08/03/2005EP1560221A2 Semiconductor memory device
08/03/2005EP1488427B1 A volumetric data storage apparatus comprising a plurality of stacked matrix-addressable memory devices
08/03/2005EP1397806B1 Identification of an integrated circuit from its physical manufacture parameters
08/03/2005CN1650270A Destructive-read random access memory system buffered with destructive-read memory cache
08/03/2005CN1649026A Semiconductor memory device
08/02/2005US6925030 Nonvolatile ferroelectric memory device with split word lines
08/02/2005US6925019 Method and system for accelerating coupling of digital signals
08/02/2005US6924690 Voltage switching circuit
08/02/2005US6924670 Complementary input dynamic muxed-decoder
08/02/2005US6924663 Programmable logic device with ferroelectric configuration memories
07/2005
07/28/2005WO2005041270A3 Mram array with segmented word and bit lines
07/28/2005WO2005041055A3 Echo clock on memory system having wait information
07/28/2005US20050166009 Integrated circuit random access memory capable of automatic internal refresh of memory array
07/28/2005US20050164748 Mobile communication terminal and communication system
07/28/2005US20050163277 Shift register for safely providing a configuration bit
07/28/2005US20050162966 Semiconductor device and manufacturing method thereof
07/28/2005US20050162965 Acess control apparatus, access control method, and access control program
07/28/2005US20050162964 Dynamic semiconductor memory device and power saving mode of operation method of the same
07/28/2005US20050162960 Semiconductor integrated circuit device
07/28/2005US20050162946 Stacked layered type semiconductor memory device
07/28/2005US20050162943 Method and apparatus for standby power reduction in semiconductor devices
07/28/2005US20050162920 Circuit and method for reducing leakage current in a row driver circuit in a flash memory during a standby mode of operation
07/28/2005US20050162911 Nonvolatile semiconductor memory device
07/28/2005US20050162891 Ferroelectric memory device and method of reading a ferroelectric memory
07/28/2005US20050162205 Device and method for setting an initial value
07/28/2005DE10123514B4 Halbleiter-Speicherbaustein Semiconductor memory device
07/27/2005EP1557841A2 Multilevel Resistive Memory device and its writing erasing method
07/27/2005CN1647211A Semiconductor storing device
07/27/2005CN1647205A Memory chip architecture having non-rectangular memory banks and method for arranging memory banks
07/27/2005CN1645511A Stacked layered type semiconductor memory device
07/27/2005CN1212621C Flash memory wordline tracking across whole chip
07/27/2005CN1212620C Trimming method and system for wordline booster to minimize process variation of boosted wordline voltage
07/26/2005US6922367 Data strobe synchronization circuit and method for double data rate, multi-bit writes
07/21/2005US20050160250 Method and apparatus of controlling electric power for translation lookaside buffer
07/21/2005US20050157586 Arrangement comprising a memory device and a program-controlled unit
07/21/2005US20050157585 Memory control device and memory control method
07/21/2005US20050157582 Semiconductor memory device with reduced power consumption for refresh operation
07/21/2005US20050157580 Semiconductor memory device and method of operating same
07/21/2005US20050157579 Memory device supporting a dynamically configurable core organization
07/21/2005US20050157578 Semiconductor memory device
07/21/2005US20050157556 Nonvolatile memory
07/21/2005US20050157553 Integrated memory device with multi-sector selection commands
07/21/2005DE102004040506A1 Adressierschaltung für ein Kreuzungspunkt-Speicherarray, das Kreuzungspunkt-Widerstandselemente umfasst Addressing circuitry comprises a cross-point memory array, the cross point resistor elements
07/20/2005CN1643616A A volumetric data storage apparatus comprising a plurality of stacked matrix-addressable memory devices
07/20/2005CN1643610A Asynchronous interface circuit and method for a pseudo-static memory device
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