Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 8 - Arrangements for selecting an address in a digital store
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
06/2005
06/22/2005EP1543411A2 Processor with explicit information on information to be secured in sub-program branches
06/22/2005CN1629974A Memory circuit and method of generating the same
06/21/2005US6910096 SDRAM with command decoder coupled to address registers
06/21/2005US6909665 Semiconductor memory device having high-speed input/output architecture
06/21/2005US6909664 Semiconductor memory device with simplified control of column switches
06/21/2005US6909663 Multiport memory with twisted bitlines
06/21/2005US6909662 Data read circuit in a semiconductor device featuring reduced chip area and increased data transfer rate
06/21/2005US6909660 Random access memory having driver for reduced leakage current
06/21/2005US6909656 PCRAM rewrite prevention
06/21/2005US6909647 Semiconductor device having redundancy circuit
06/21/2005US6909640 Block select circuit in a flash memory device
06/21/2005US6909635 Programmable memory cell using charge trapping in a gate oxide
06/21/2005US6909627 Apparatus turning on word line decoder by reference bit line equalization
06/21/2005US6909623 Dense content addressable memory cell
06/16/2005WO2005029498A3 Nanoscale wire coding for stochastic assembly
06/16/2005WO2005020494A3 Method and apparatus for providing interprocessor communications using shared memory
06/16/2005WO2005006394A3 Circuit for testing and fine tuning integrated circuit (switch control circuit)
06/16/2005WO2004021355A3 Electronic device with data storage device
06/16/2005US20050128859 Delay circuit, ferroelectric memory device and electronic equipment
06/16/2005US20050128858 Negative word line driver
06/16/2005US20050128857 X address extractor and memory for high speed operation
06/16/2005US20050128856 X address extractor and method for extracting X-address in memory device
06/16/2005US20050128855 Self timed bit and read/write pulse stretchers
06/16/2005US20050128854 Synchronous controlled, self-timed local SRAM block
06/16/2005US20050128853 Semiconductor device including multi-chip
06/16/2005US20050128845 Device and method for decoding an address word into word-line signals
06/16/2005US20050128833 Semiconductor memory device having access time control circuit
06/16/2005US20050128830 Semiconductor memory device
06/16/2005US20050128828 Methods and circuits for latency control in accessing memory devices
06/16/2005US20050128820 Circuit for detecting negative word line voltage
06/16/2005US20050128818 Memory circuit and method of generating the same
06/16/2005US20050128807 Nand memory array incorporating multiple series selection devices and method for operation of same
06/16/2005US20050128786 Semiconductor memory device
06/16/2005US20050128779 Imprint suppression circuit scheme
06/16/2005US20050127969 Circuit of controlling pulse width and method of controlling the same
06/16/2005DE102004051158A1 Integrierter Halbleiterspeicher Integrated semiconductor memory
06/15/2005EP1542284A1 Magnetic non-volatile memory element
06/15/2005EP1542234A2 Method for designing an extented memory array using a plurality of serial memories
06/15/2005EP1542233A1 Serial memory comprising means for protecting an extended memory range during a write operation
06/15/2005EP1542130A1 Serial memory comprising an extended memory space integration means
06/15/2005EP1540654A1 Disc with temporary disc definition structure (tdds) and temporary defect list (tdfl), and method of and apparatus for managing defect in the same
06/15/2005EP1242868A4 Organization of blocks within a nonvolatile memory unit to effectively decrease sector write operation time
06/15/2005CN1627445A Delay circuit, ferroelectric memory device and electronic equipment
06/15/2005CN1627444A 半导体存储器件 A semiconductor memory device
06/15/2005CN1627443A Methods of activating word line segments enabled by row addresses and semiconductor memory devices
06/15/2005CN1627441A Latch circuit and synchronous memory including the same
06/15/2005CN1206733C Semiconductor integrated circuit
06/14/2005US6906979 Semiconductor memory device having bit line kicker
06/14/2005US6906978 Flexible integrated memory
06/14/2005US6906970 Address counter strobe test mode device
06/14/2005US6906966 Fast discharge for program and verification
06/14/2005US6906960 Semiconductor memory device
06/14/2005US6906958 Word-line voltage generator
06/14/2005US6906955 Flash memory with RDRAM interface
06/14/2005US6906942 Programmable mask ROM building element and process of manufacture
06/09/2005WO2005052947A1 Compressed event counting technique and application to a flash memory system
06/09/2005WO2005052946A1 Embedded memory with security row lock protection
06/09/2005WO2005001899A3 Non-volatile electromechanical field effect devices and circuits using same and methods of forming same
06/09/2005US20050125615 Methods and apparatus for writing an LRU bit
06/09/2005US20050125594 Memory with synchronous bank architecture
06/09/2005US20050122830 Semiconductor memory device and data read method of the same
06/09/2005US20050122828 Magnetic switching device and memory using the same
06/09/2005US20050122827 Active matrix display and driving method therefor
06/09/2005US20050122826 Selectable memory word line deactivation
06/09/2005US20050122824 Packet addressing programmable dual port memory devices and related methods
06/09/2005US20050122822 Random access memory with optional inaccessible memory cells
06/09/2005US20050122810 Methods and systems for dynamically selecting word line off times and/or bit line equalization start times in memory devices
06/09/2005US20050122802 Semiconductor storage device formed to optimize test technique and redundancy technology
06/09/2005US20050122799 Semiconductor integrated circuit provided with semiconductor memory circuit having redundancy function and method for transferring address data
06/09/2005US20050122782 Semiconductor memory device
06/09/2005US20050122761 FeRAM having wide page buffering function
06/09/2005US20050122149 Duty cycle correction circuits suitable for use in delay-locked loops and methods of correcting duty cycles of periodic signals
06/09/2005US20050122147 Circuit for controlling pulse width
06/09/2005US20050121810 Dual port memory core cell architecture with matched bit line capacitances
06/08/2005EP1538633A2 Flash memory device and method for programming the same
06/08/2005EP1538600A2 Display controller with display memory circuit
06/08/2005EP1538498A2 Address decoder and method to decode addresses
06/08/2005EP1537583A1 Device writing to a plurality of rows in a memory matrix simultaneously
06/08/2005EP1537483A1 A memory circuit comprising a non-volatile ram and a ram
06/08/2005CN1624805A Shift register of safety providing configuration bit
06/08/2005CN1624798A Methods and apparatus for writing an LRU bit
06/08/2005CN1205617C Buff circuit
06/07/2005US6903993 Memory cell with fuse element
06/07/2005US6903983 Semiconductor integrated circuit device and read start trigger signal generating method therefor
06/07/2005US6903982 Bit line segmenting in random access memories
06/07/2005US6903956 Semiconductor memory device
06/02/2005WO2005050657A1 Method for operating a data storage apparatus employing passive matrix addressing
06/02/2005WO2005050655A1 Latch scheme with invalid command detector
06/02/2005WO2005024640A3 Circulator chain memory command and address bus topology
06/02/2005US20050117445 Semiconductor integrated circuit
06/02/2005US20050117443 EEPROM cell and EEPROM device with high integration and low source resistance and method of manufacturing the same
06/02/2005US20050117442 Integrated semiconductor memory
06/02/2005US20050117439 Ferroelectric film, method of manufacturing ferroelectric film, ferroelectric capacitor, and ferroelectric memory
06/02/2005US20050117434 Semiconductor memory device
06/02/2005US20050117433 Semiconductor device
06/02/2005US20050117427 Dense content addressable memory cell
06/02/2005US20050117416 Address decoding circuit and method for addressing a regular memory area and a redundant memory area in a memory circuit
06/02/2005US20050117413 Semiconductor device having automatic controlled delay circuit and method therefor
06/02/2005US20050117402 Address input buffer of differential amplification type in semiconductor memory device
06/02/2005US20050117399 Flash memory devices and methods for programming the same
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