Patents
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
03/2005
03/03/2005US20050047197 Semiconductor memory device including 4TSRAMs
03/03/2005US20050047187 Integrated circuit memory devices reducing propagation delay differences between signals transmitted to separate spaced-apart memory blocks therein
03/03/2005DE19723432B4 Halbleiterspeicher-Bauelement mit Bänken A semiconductor memory device with benches
03/03/2005DE19503988B4 Halbleiterspeichervorrichtung A semiconductor memory device
03/03/2005DE10333280A1 Halbleiter-Speicherbauelement, und Verfahren zum Betrieb eines Halbleiter-Speicherbauelements A semiconductor memory device, and method for operating a semiconductor memory device
03/03/2005DE102004011741A1 Halbleiterspeicherschaltung und zugehöriger Halbleiterspeicherbaustein A semiconductor memory circuit and related semiconductor memory device
03/03/2005DE10020416B4 High-Pegel-Erzeugungsschaltkreis für eine Halbleiterspeichervorrichtung High-level generating circuit for a semiconductor memory device
03/02/2005CN1589438A Method employed by a base station for transferring data
03/01/2005US6862672 Semiconductor memory device and method of controlling same
03/01/2005US6862251 Semiconductor memory device
03/01/2005US6862248 Method for masking ringing in DDR SDRAM
03/01/2005US6862245 Dual port static memory cell and semiconductor memory device having the same
03/01/2005US6862222 Non-volatile memory device with erase address register
03/01/2005US6862205 Semiconductor memory device
03/01/2005US6862202 Low power memory module using restricted device activation
02/2005
02/24/2005WO2005017903A1 Hub component for connection to one or more memory modules
02/24/2005US20050044337 Method and apparatus for address decoding of embedded DRAM devices
02/24/2005US20050044302 Non-standard dual in-line memory modules with more than two ranks of memory per module and multiple serial-presence-detect devices to simulate multiple modules
02/24/2005US20050044280 Software and method that enables selection of one of a plurality of online service providers
02/24/2005US20050041520 Semiconductor memory device
02/24/2005US20050041513 Multi-level semiconductor memory architecture and method of forming the same
02/24/2005US20050041510 Method and apparatus for providing interprocessor communications using shared memory
02/24/2005US20050041507 Fuse circuit
02/24/2005US20050041501 Memory device having a configurable oscillator for refresh operation
02/24/2005US20050041485 Adjustable timing circuit of an integrated circut
02/24/2005US20050041478 Method of controlling the operation of non-volatile semiconductor memory chips
02/24/2005US20050041475 Program voltage generation circuit for stably programming flash memory cell and method of programming flash memory cell
02/24/2005US20050041453 Method and apparatus for reading and writing to solid-state memory
02/24/2005DE10063732B4 Halbleiterspeicherbauelement mit hierarchischer Wortleitungsstruktur Semiconductor memory device with a hierarchical word line structure
02/24/2005DE10061604B4 Halbleiterspeicher, der mit einem Reihenadressendecodierer versehen ist, der eine reduzierte Signalausbreitungsverzögerungszeit hat A semiconductor memory, which is provided with a row address decoder, which has a reduced signal propagation delay time
02/23/2005EP1508901A1 Memory circuit having nonvolatile identification memory and associated process
02/23/2005CN1585124A Fuse circuit
02/23/2005CN1584774A 半导体集成电路 The semiconductor integrated circuit
02/22/2005US6859412 Circuit for controlling driver strengths of data and data strobe in semiconductor device
02/22/2005US6859410 Tree decoder structure particularly well-suited to interfacing array lines having extremely small layout pitch
02/22/2005US6859403 Semiconductor memory device capable of overcoming refresh disturb
02/22/2005US6859386 Semiconductor memory device with memory cell having low cell ratio
02/22/2005US6859384 Semiconductor memory device having two-transistor, one-capacitor type memory cells of high data holding characteristic
02/17/2005WO2005015564A1 Non-standard dual in-line memory modules with more than two ranks of memory per module and multiple serial-presence-detect devices to simulate multiple modules
02/17/2005US20050038952 Timing control method for operating synchronous memory
02/17/2005US20050036581 Shift register unit and signal driving circuit using the same
02/17/2005US20050036394 Semiconductor device having a data latching or storing function
02/17/2005US20050036392 Architecture and fabrication method of a vertical memory cell
02/17/2005US20050036391 Nonvolatile semiconductor memory apparatus and the operation method
02/17/2005US20050036386 Method and apparatus for synchronization of row and column access operations
02/17/2005US20050036385 System for reducing row periphery power consumption in memory devices
02/17/2005US20050036363 High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines
02/17/2005US20050036360 Apparatus turning on word line decoder by reference bit line equalization
02/17/2005US20050036358 Nonvolatile ferroelectric memory device with split word lines
02/17/2005US20050036350 Memory module
02/17/2005US20050035972 Memory control device and method
02/17/2005US20050035807 Level down converter
02/17/2005US20050035800 Percent-of-clock delay circuits with enhanced phase jitter immunity
02/17/2005US20050035403 System with meshed power and signal buses on cell array
02/16/2005EP1058930A4 A memory supporting multiple address protocols
02/16/2005CN1581358A Memory and its driving method
02/15/2005US6856573 Column decoder configuration for a 1T/1C memory
02/15/2005US6856572 Multi-headed decoder structure utilizing memory array line driver with dual purpose driver device
02/15/2005US6856571 Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure
02/15/2005US6856566 Timer circuit and semiconductor memory incorporating the timer circuit
02/15/2005US6856563 Semiconductor memory device for enhancing bitline precharge time
02/15/2005US6856531 Hacker-proof one time programmable memory
02/15/2005US6856204 Phase locked loop circuit having wide locked range and semiconductor integrated circuit device having the same
02/15/2005US6855564 Magnetic random access memory having transistor of vertical structure with writing line formed on an upper portion of the magnetic tunnel junction cell
02/10/2005WO2005013357A1 Method of manufacturing multi-level contacts by sizing of contact sizes in integrated circuits
02/10/2005WO2005013282A1 Wordline latching in semiconductor memories
02/10/2005US20050033903 Integrated circuit device
02/10/2005US20050030828 Nonvolatile semiconductor memory device and data write method thereof
02/10/2005US20050030819 Method and apparatus for standby power reduction in semiconductor devices
02/10/2005US20050030802 Memory module including an integrated circuit device
02/10/2005US20050030783 Dynamic RAM and semiconductor device
02/10/2005US20050029681 Semiconductor memory device and method for producing the same
02/10/2005DE10345550B3 Computer memory device with several random-access memory modules divided into disjunctive module groups each having memory cells organized in disjunctive cell groups with simultaneous write-in and read-out
02/10/2005DE102004034758A1 Mehrblock-Speicherbaustein und zugehöriges Betriebsverfahren Multi-block memory device and operating method thereof
02/10/2005DE102004033450A1 Flash memory device e.g. non-volatile EEPROM, for storing information, has variable bit line voltage generating circuit generating variable bit line voltage changed in response to supply voltage and proportional to supply voltage
02/09/2005CN1577862A Non-volatile semiconductor memory device, electronic card and electronic device
02/09/2005CN1577623A Data pass control device for masking write ringing in ddr sdram and method thereof
02/09/2005CN1577622A Memory circuit, display device and electronic equipment each comprising the same
02/09/2005CN1577613A Semiconductor memory device capable of accessing data in continuous burst mode regardless of location of accessed data
02/09/2005CN1577475A Display driver, display device and driving method
02/09/2005CN1188863C Synchronous memory module with selective clock terminal joint and memory thereof
02/08/2005US6854047 Data storage device and data transmission system using the same
02/08/2005US6854030 Integrated circuit device having a capacitive coupling element
02/08/2005US6853601 Device and method for repairing a memory array by storing each bit in multiple memory cells in the array
02/08/2005US6853597 Integrated circuits with parallel self-testing
02/08/2005US6853591 Circuit and method for decreasing the required refresh rate of DRAM devices
02/08/2005US6853588 First-in first-out memory circuit and method for executing same
02/08/2005US6853582 Nonvolatile memory with controlled voltage boosting speed
02/03/2005WO2005010890A1 Programmable chip select
02/03/2005WO2004061859A3 Stochastic assembly of sublithographic nanoscale interfaces
02/03/2005US20050028061 Data storage method with error correction
02/03/2005US20050024985 Delay locked loop control circuit
02/03/2005US20050024979 Metal-insulator-metal capacitor and interconnecting structure
02/03/2005US20050024976 Content addressable memory device
02/03/2005US20050024975 Compact decode and multiplexing circuitry for a multi-port memory having a common memory interface
02/03/2005US20050024974 Semiconductor memory device
02/03/2005US20050024970 Device having a memory array storing each bit in multiple memory cells
02/03/2005US20050024945 Programmable memory address and decode circuits with low tunnel barrier interpoly insulators
02/03/2005US20050024923 Gain cell memory having read cycle interlock
02/03/2005DE69333631T2 Halbleiterspeicheranordnung A semiconductor memory device