Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 8 - Arrangements for selecting an address in a digital store
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
09/2005
09/15/2005DE69333606T2 Nichtflüchtiger Halbleiterspeicher mit elektrisch und gemeinsam löschbaren Eigenschaften A non-volatile semiconductor memory having electrically and collectively erasable characteristics
09/15/2005DE19650303B4 Integrierte Speicherschaltung An integrated memory circuit
09/15/2005DE102004005667A1 Integrierter Halbleiterspeicher mit temperaturabhängiger Spannungserzeugung Integrated semiconductor memory with temperature-dependent voltage generating
09/14/2005EP1575298A1 Data storage apparatus, data storage control apparatus, data storage control method, and data storage control program
09/14/2005EP1573742A2 Magnetoresistive memory cell array and mram memory comprising such array
09/14/2005EP1573541A2 Data storage method with error correction
09/14/2005CN1667750A Apparatus for generating internal clock signal
09/14/2005CN1667748A Semiconductor integrated circuit device
09/14/2005CN1667685A Method for driving data line, and display device and liquid crystal display device using the same
09/13/2005US6944739 Register bank
09/13/2005US6944091 Latency control circuit and method of latency control
09/13/2005US6944088 Apparatus and method for generating memory access signals, and memory accessed using said signals
09/13/2005US6944087 Method and apparatus for off boundary memory access
09/13/2005US6944086 Semiconductor memory device
09/13/2005US6944080 Dynamic random access memory(DRAM) capable of canceling out complimentary noise developed in plate electrodes of memory cell capacitors
09/13/2005US6944059 High voltage generation and regulation circuit in a memory device
09/13/2005US6944045 Data holding apparatus and data read out method
09/13/2005US6943603 Pulse generating circuit and semiconductor device provided with same
09/09/2005WO2005057586A3 Nand memory array incorporating multiple series selection devices and method for operation of same
09/08/2005US20050195977 Semiconductor memory apparatus
09/08/2005US20050195716 Disc with temporary disc definition structure (TDDS) and temporary defect list (TDFL), and method of and apparatus for managing defect in the same
09/08/2005US20050195680 Semiconductor storage device
09/08/2005US20050195678 Apparatus for editing configuration of digital mixer
09/08/2005US20050195677 Method and apparatus for optimizing timing for a multi-drop bus
09/08/2005US20050195663 Delay locked loop in semiconductor memory device
09/08/2005US20050195015 Low voltage boosted analog transmission gate
09/08/2005US20050195004 Delay locked loop in semiconductor memory device and its clock locking method
09/08/2005DE102004007661A1 Verfahren zur Optimierung eines Layouts von Versorgungsleitungen A method for optimizing a layout of power supply lines
09/07/2005CN1666291A Wordline latching in semiconductor memories
09/07/2005CN1664956A Delay locked loop in semiconductor memory device and its clock locking method
09/06/2005US6940775 Integrated dynamic memory having a control circuit for controlling a refresh mode for memory cells
09/06/2005US6940774 Integrated dynamic memory and operating method
09/06/2005US6940770 Method for precharging word and bit lines for selecting memory cells within a memory array
09/06/2005US6940762 Semiconductor memory device including MOS transistor having a floating gate and a control gate
09/06/2005US6940759 Group erasing system for flash array with multiple sectors
09/06/2005US6940749 MRAM array with segmented word and bit lines
09/06/2005US6940163 On die voltage regulator
09/01/2005US20050193356 Nanoscale interconnection interface
09/01/2005US20050190640 Method and apparatus for improving cycle time in a quad data rate sram device
09/01/2005US20050190637 Quantum memory and information processing method using the same
09/01/2005US20050190636 Semiconductor device having storage circuit which stores data in nonvolatile manner by using fuse element
09/01/2005US20050190634 Memory system using simultaneous bi-directional input/output circuit on an address bus line
09/01/2005US20050190631 Method for bus capacitance reduction
09/01/2005US20050190629 Method and apparatus for testing circuit units to be tested with different test mode data sets
09/01/2005US20050190604 Semiconductor memory device
09/01/2005DE102005005342A1 Busanordnung, Master- und Slave-Einheit sowie Datenlese- und Datenübertragungsverfahren Bus arrangement, master and slave unit and data read and data transfer method
08/2005
08/31/2005CN1661801A Ultraviolet erasing semiconductor memory
08/31/2005CN1661726A Semiconductor memory device
08/31/2005CN1217342C Multichannel memory management system
08/31/2005CN1217266C Memory address producing device, moving station and data read/write method
08/30/2005US6938166 Method of downloading of data to an MPEG receiver/decoder and MPEG transmission system for implementing the same
08/30/2005US6937533 Semiconductor integrated circuit provided with semiconductor memory circuit having redundancy function and method for transferring address data
08/30/2005US6937509 Data storage device and method of forming the same
08/30/2005US6937495 Current sensing method and apparatus particularly useful for a memory array of cells having diode-like characteristics
08/30/2005US6937248 Pixel array with indirectly associated memory
08/30/2005US6937247 Memory control device and method
08/30/2005US6936889 Semiconductor device and method for testing semiconductor device
08/30/2005CA2284153C Method of downloading of data to an mpeg receiver/decoder and mpeg transmission system for implementing the same
08/25/2005WO2005078729A2 High voltage driver circuit with fast reading operation
08/25/2005US20050185752 Shift register for pulse-cut clock signal
08/25/2005US20050185572 Fast reading, low consumption memory device and reading method thereof
08/25/2005US20050185500 Domain crossing device
08/25/2005US20050185498 Timing calibration pattern for SLDRAM
08/25/2005US20050185497 Semiconductor memory device
08/25/2005US20050185496 Intelligent solid state disk
08/25/2005US20050185495 Semiconductor memory device having a single input terminal to select a buffer and method of testing the same
08/25/2005US20050185493 Data transfer method and system
08/25/2005US20050185481 Redundancy relieving circuit
08/25/2005US20050185465 Memory device
08/25/2005US20050185452 Pulsed write techniques for magneto-resistive memories
08/25/2005US20050184779 Open-loop digital duty cycle correction circuit without DLL
08/25/2005US20050184380 Semiconductor device and a memory system including a plurality of IC chips in a common package
08/25/2005CA2555581A1 Non-switching pre-and post-disturb compensational pulses
08/24/2005EP1566810A2 Resistive memory device with stable writing
08/24/2005CN1658171A Faster write operations to nonvolatile memory by manipulation of frequently accessed sectors
08/23/2005US6934795 Content addressable memory with programmable word width and programmable priority
08/23/2005US6934216 Semiconductor memory device
08/23/2005US6934214 Semiconductor memory device having a hierarchical I/O structure
08/23/2005US6934201 Asynchronous, high-bandwidth memory component using calibrated timing elements
08/23/2005US6934196 Memory module with magnetoresistive elements and a method of reading data from in-row and in-column directions
08/23/2005CA2294027C Method and apparatus for audibly indicating when a predetermined location has been encountered in stored data
08/18/2005WO2005076282A1 Semiconductor storage device
08/18/2005US20050182914 Synchronous dram system with control data
08/18/2005US20050180252 Method and apparatus for saving current in a memory device
08/18/2005US20050180251 Method for optimizing a layout of supply lines
08/18/2005US20050180250 Data packet buffering system with automatic threshold optimization
08/18/2005US20050180248 Word line arrangement having multi-layer word line segments for three-dimensional memory array
08/18/2005US20050180247 Word line arrangement having multi-layer word line segments for three-dimensional memory array
08/18/2005US20050180246 High speed DRAM architecture with uniform access latency
08/18/2005US20050180244 Word line arrangement having segmented word lines
08/18/2005US20050180243 Semiconductor device
08/18/2005US20050180226 Voltage output control apparatus and method
08/18/2005US20050180221 Data storage unit, data storage controlling apparatus and method, and data storage controlling program
08/18/2005US20050180199 SRAM cell design for soft error rate immunity
08/18/2005CA2554116A1 Method and apparatus for secure data storage
08/17/2005EP1564948A1 Digital transmission with controlled rise and fall times
08/17/2005EP1564749A2 Multi-port memory based on DRAM core
08/17/2005EP1564748A2 Multi-port memory based on DRAM core
08/17/2005EP1564747A1 Semiconductor memory device comprising simultaneous block activation means and method of testing semiconductor memory device
08/17/2005EP1564746A2 Image memory architecture for achieving high speed access
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