| Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368) |
|---|
| 03/16/2006 | DE10110707B4 Ferroelektrischer Speicher mit Referenzzellen-Auswahlschaltung und 2T1C-Speicherzellen A ferroelectric memory with reference cell selection circuit and 2T1C memory cells |
| 03/15/2006 | EP1634296A2 Non-volatile electromechanical field effect devices and circuits using same and methods of forming same |
| 03/15/2006 | CN1747057A Memory device for reducing leakage current |
| 03/14/2006 | US7013374 Integrated memory and method for setting the latency in the integrated memory |
| 03/14/2006 | US7012851 Nonvolatile ferroelectric memory device with split word lines |
| 03/14/2006 | US7012850 High speed DRAM architecture with uniform access latency |
| 03/14/2006 | US7012848 Semiconductor integrated circuit device |
| 03/14/2006 | US7012838 Nonvolatile semiconductor memory device supplying proper program potential |
| 03/14/2006 | US7012837 Method for erasing/programming a non-volatile electrically erasable memory |
| 03/09/2006 | US20060050603 Parallel asynchronous propagation pipeline structure and methods to access multiple memory arrays |
| 03/09/2006 | US20060050602 Apparatus and Method for Generating a Variable-Frequency Clock |
| 03/09/2006 | US20060050601 Semiconductor memory device |
| 03/09/2006 | US20060050600 Circuit for verifying the write speed of SRAM cells |
| 03/09/2006 | US20060050599 Memory device and method for burn-in test |
| 03/09/2006 | US20060050598 Memory using variable tunnel barrier widths |
| 03/09/2006 | US20060050597 Active termination control through module register |
| 03/09/2006 | US20060050596 Dynamic monitoring of activation of G-protein coupled receptor (GPCR) and receptor tyrosine kinase (RTK) in living cells using real-time microelectronic cell sensing technology |
| 03/09/2006 | US20060050595 Semiconductor memory device with reduced leak current |
| 03/09/2006 | US20060050594 Flash memory device and method of erasing flash memory cell thereof |
| 03/09/2006 | US20060050593 Non-volatile memory device |
| 03/09/2006 | US20060050592 Compact module system and method |
| 03/09/2006 | US20060050591 Address coding method and address decoder for reducing sensing noise during refresh operation of memory device |
| 03/09/2006 | DE102005041034A1 Memory module e.g. single in-line memory module, has selection circuit which outputs non-periodic clock signal to memory and register, and register which controls address data of memory in synchronization with received signal |
| 03/08/2006 | EP1632950A1 Non-volatile memory device with improved initialization readout speed |
| 03/08/2006 | EP1632845A2 Processor with a register file that supports multiple-issue execution |
| 03/08/2006 | CN1745433A Zone boundary adjustment for defects in non-volatile memories |
| 03/07/2006 | US7009911 Memory array decoder |
| 03/07/2006 | US7009910 Semiconductor memory having a flexible dual-bank architecture with improved row decoding |
| 03/07/2006 | US7009909 Line drivers that use minimal metal layers |
| 03/07/2006 | US7009908 Decoding device |
| 03/07/2006 | US7009907 FeRAM having sensing voltage control function |
| 03/07/2006 | US7009906 Semiconductor memory device having easily redesigned memory capacity |
| 03/07/2006 | US7009899 Bit line precharge signal generator for memory device |
| 03/07/2006 | US7009895 Method for skip over redundancy decode with very low overhead |
| 03/07/2006 | US7009893 Range selectable address decoder and frame memory device for processing graphic data at high speed using the same |
| 03/07/2006 | US7009885 Circuit and method for reducing leakage current in a row driver circuit in a flash memory during a standby mode of operation |
| 03/07/2006 | US7009441 Phase multiplier circuit |
| 03/02/2006 | WO2006023391A1 Memory device having staggered memory operations |
| 03/02/2006 | US20060044934 Cluster based non-volatile memory translation layer |
| 03/02/2006 | US20060044933 Burst read addressing in a non-volatile memory device |
| 03/02/2006 | US20060044932 Method for routing data paths in a semiconductor chip with a plurality of layers |
| 03/02/2006 | US20060044931 Delay-locked loop having a pre-shift phase detector |
| 03/02/2006 | US20060044930 Apparatus with equalizing voltage generation circuit and methods of use |
| 03/02/2006 | US20060044929 Magnetic shielding for magnetic random access memory card |
| 03/02/2006 | US20060044928 Drive method for MEMS devices |
| 03/02/2006 | US20060044927 Memory module, memory unit, and hub with non-periodic clock and methods of using the same |
| 03/02/2006 | US20060044926 Method and system for accessing performance parameters in memory devices |
| 03/02/2006 | US20060044925 Limited output address register technique providing selectively variable write latency in DDR2 (double data rate two) integrated circuit memory devices |
| 03/02/2006 | US20060044924 Semiconductor memory device |
| 03/02/2006 | US20060044923 Programming circuits and methods for multimode non-volatile memory devices |
| 03/02/2006 | US20060044922 Word line driver circuitry and methods for using the same |
| 03/02/2006 | US20060044921 Memory devices having reduced coupling noise between wordlines |
| 03/02/2006 | US20060044920 Serial memory address decoding scheme |
| 03/02/2006 | US20060044919 Non-volatile memory device and erasing method therefor |
| 03/02/2006 | US20060044918 Semiconductor memory devices having column redundancy circuits therein that support multiple memory blocks |
| 03/02/2006 | US20060044889 Internal voltage level control circuit and semiconductor memory device as well as method of controlling the same |
| 03/02/2006 | DE10231954B4 Schaltungsbaustein mit Zeitsteuerung Mounted module timing |
| 03/01/2006 | EP1630819A2 Three-dimensional memory array |
| 03/01/2006 | CN1742341A Hardware security device for magnetic memory cells |
| 03/01/2006 | CN1244235C Method of and apparatus for transmitting data for interactive TV applications |
| 02/28/2006 | USRE38997 Information storage and information processing system utilizing state-designating member provided on supporting card surface which produces write-permitting or write-inhibiting signal |
| 02/28/2006 | US7006404 Memory device with increased data throughput |
| 02/28/2006 | US7006403 Self timed bit and read/write pulse stretchers |
| 02/28/2006 | US7006402 Multi-port memory device |
| 02/28/2006 | US7006369 Design and use of a spacer cell to support reconfigurable memories |
| 02/28/2006 | US7005698 Split gate flash memory cell |
| 02/23/2006 | US20060039232 Read command triggered synchronization circuitry |
| 02/23/2006 | US20060039231 Method of data flow control for a high speed memory |
| 02/23/2006 | US20060039230 Semiconductor memory device |
| 02/23/2006 | US20060039229 Semiconductor storage device |
| 02/23/2006 | US20060039228 Method and apparatus for memory device wordline |
| 02/23/2006 | US20060039226 Low power manager for standby operation of a memory system |
| 02/23/2006 | US20060039223 Semiconductor memory device, control method thereof, and control method semiconductor device |
| 02/23/2006 | US20060039213 Integrated circuit I/O using a high performance bus interface |
| 02/23/2006 | US20060039205 Reducing the number of power and ground pins required to drive address signals to memory modules |
| 02/23/2006 | US20060039204 Method and apparatus for encoding memory control signals to reduce pin count |
| 02/23/2006 | US20060039178 Device having a memory array storing each bit in multiple memory cells |
| 02/23/2006 | US20060039174 Memory module with termination component |
| 02/22/2006 | EP1627392A1 Circuit configuration for a current switch of a bit/word line of a mram device |
| 02/21/2006 | US7003636 Memory control circuit |
| 02/21/2006 | US7002875 Semiconductor memory |
| 02/21/2006 | US7002874 Dual word line mode for DRAMs |
| 02/21/2006 | US7002873 Memory array with staged output |
| 02/21/2006 | US7002872 Semiconductor memory device with a decoupling capacitor |
| 02/21/2006 | US7002871 Asynchronous pseudo SRAM and access method therefor |
| 02/21/2006 | US7002868 High-speed, two-port dynamic random access memory (DRAM) with a late-write configuration |
| 02/21/2006 | US7002867 Refresh control circuit for ICs with a memory array |
| 02/21/2006 | US7002861 Memory device for controlling programming setup time |
| 02/21/2006 | US7002860 Multilevel register-file bit-read method and apparatus |
| 02/21/2006 | US7002857 Semiconductor device having automatic controlled delay circuit and method therefor |
| 02/21/2006 | US7002856 Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions |
| 02/21/2006 | US7002855 Leakage tolerant register file |
| 02/21/2006 | US7002854 Internal voltage level control circuit and semiconductor memory device as well as method of controlling the same |
| 02/21/2006 | US7002826 Semiconductor memory device |
| 02/21/2006 | US7002825 Word line arrangement having segmented word lines |
| 02/21/2006 | US7002822 Content addressable memory device |
| 02/21/2006 | US7002367 Method and apparatus for low capacitance, high output impedance driver |
| 02/21/2006 | US7002258 Dual port memory core cell architecture with matched bit line capacitances |
| 02/16/2006 | WO2006017461A2 Byte enable logic for memory |
| 02/16/2006 | WO2006017416A2 Programmable semi-fusible link read only memory and method of margin testing same |