Patents
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
02/2005
02/03/2005DE10015253B4 Halbleiter-Speichervorrichtung und Schreibdaten-Maskierungsverfahren dafür The semiconductor memory device and write data masking method thereof
02/02/2005CN1575495A Memory arrangement
02/02/2005CN1574099A Bidirectional shift register and display device incorporating same
02/02/2005CN1574087A Latency control circuit and method of latency control
02/02/2005CN1574085A Method and apparatus for rapidly storing data in memory cell without voltage loss
02/02/2005CN1574082A Control device for controlling self refresh operation in synchronous semiconductor memory device
02/02/2005CN1574063A Memory device with selectively connectable segmented bit line member and method of driving the same
02/02/2005CN1187825C Semiconductor storing device with shorter time delay of data transmission
02/02/2005CN1187757C Synchronization device for synchronous dynamic random-access memory
02/01/2005US6850456 Subarray control and subarray cell access in a memory module
02/01/2005US6850454 Semiconductor memory device with reduced current consumption during standby state
02/01/2005US6850446 Memory cell sensing with low noise generation
02/01/2005US6850443 Wear leveling techniques for flash EEPROM systems
02/01/2005US6850431 Pulsed write techniques for magneto-resistive memories
02/01/2005US6849863 Quantum memory and information processing method using the same
01/2005
01/27/2005WO2005008673A1 Data strobe synchronization circuit and method for double data rate, multi-bit writes
01/27/2005US20050021922 Programmable chip select
01/27/2005US20050018807 Shift register
01/27/2005US20050018529 Fully hidden refresh dynamic random access memory
01/27/2005US20050018525 Semiconductor device and method for fabricating the same
01/27/2005US20050018523 Dynamic memory word line driver scheme
01/27/2005US20050018521 Methods and devices for accessing a memory using multiple separate address mapped temporary storage areas
01/27/2005US20050018489 Non-volatile semiconductor memory device and electric device with the same
01/27/2005US20050018462 Pattern layout of transfer transistors employed in row decoder
01/27/2005US20050017065 Bidirectional shift register and display device incorporating same
01/27/2005DE102004008240A1 Verfahren und Vorrichtungen zum Bestimmen des Zustands eines Speicherelements Methods and apparatus for determining the state of a memory element
01/26/2005EP1501097A2 Memory circuit, display device and electronic equipment each comprising the same
01/26/2005EP1299885B1 Addressing of memory matrix
01/26/2005CN1571067A Ferroelectric memory
01/26/2005CN1570853A Device and method for protecting data by confusion processing of bit address wire
01/25/2005US6848040 Column address path circuit and method for memory devices having a burst access mode
01/25/2005US6847580 Method of controlling data reading capable of increasing data transfer rate in SDRAM of the posted CAS standard
01/25/2005US6847579 Semiconductor memory device
01/25/2005US6847576 Layout structures of data input/output pads and peripheral circuits of integrated circuit memory devices
01/25/2005US6847575 Semiconductor device including multi-chip
01/20/2005WO2005006394A2 Circuit for testing and fine tuning integrated circuit (switch control circuit)
01/20/2005US20050015412 Method to maintain data integrity during flash file transfer to raid controller flash using a terminal emulation program
01/20/2005US20050013180 Memory circuit, display device and electronic equipment each comprising the same
01/20/2005US20050013170 Full-swing wordline driving circuit
01/20/2005US20050013168 Non-volatile semiconductor memory device, electronic card and electronic device
01/20/2005US20050013166 Flash memory capable of utilizing one driving voltage output circuit to drive a plurality of word line drivers
01/20/2005US20050013164 Nonvolatile memory and method of driving the same
01/20/2005US20050013160 Semiconductor memory device
01/20/2005US20050013159 Semiconductor integrated circuit device
01/20/2005US20050012161 Semiconductor memory device
01/20/2005US20050012141 Asymmetric band-gap engineered nonvolatile memory device
01/19/2005EP1498903A2 High speed data access memory arrays
01/19/2005EP1497733A1 Destructive-read random access memory system buffered with destructive-read memory cache
01/19/2005EP1228510A4 Space management for managing high capacity nonvolatile memory
01/19/2005CN1185658C Memory array with address scrambling
01/18/2005US6845459 System and method to provide tight locking for DLL and PLL with large range, and dynamic tracking of PVT variations using interleaved delay lines
01/18/2005US6845458 System and method of operation of DLL and PLL to provide tight locking with large range, and dynamic tracking of PVT variations using interleaved delay lines
01/18/2005US6845061 Method for quickly detecting the state of a nonvolatile storage medium
01/18/2005US6845060 Program counting circuit and program word line voltage generating circuit in flash memory device using the same
01/18/2005US6845059 High performance gain cell architecture
01/18/2005US6845056 Semiconductor memory device with reduced power consumption
01/18/2005US6845049 Semiconductor memory device including a delaying circuit capable of generating a delayed signal with a substantially constant delay time
01/18/2005US6845047 Read circuit of nonvolatile semiconductor memory
01/18/2005US6845045 Background operation for memory cells
01/18/2005US6845025 Word line driver circuit for a content addressable memory
01/13/2005WO2005004164A1 Semiconductor storage device
01/13/2005WO2004075257A3 Memory having variable refresh control and method therefor
01/13/2005WO2004042559A3 Processor with explicit information on information to be secured in sub-program branches
01/13/2005US20050007861 System for reducing row periphery power consumption in memory devices
01/13/2005US20050007859 Memory devices including global row decoders and operating methods thereof
01/13/2005US20050007847 Method and apparatus for saving current in a memory device
01/13/2005US20050007836 Data strobe synchronization circuit and method for double data rate, multi-bit writes
01/13/2005US20050007832 High voltage generation and regulation circuit in a memory device
01/13/2005US20050006692 Flash memory device
01/13/2005DE10339665B3 Semiconductor memory device operating method, by leaving active the cells in sub-array if access is to be made to further memory cells in same memory cell array
01/13/2005DE102004027882A1 Multi-port memory device for video camera, has data line sense amplifiers sensing data read from memory cells of selected banks, and read data lines simultaneously transmitting data from amplifiers to buffers
01/13/2005DE102004027121A1 Ein Mehrfachbankchip, der mit einer Steuerung kompatibel ist, die für eine geringere Anzahl von Banken entworfen ist, und ein Verfahren zum Betreiben A multiple bank chip that is compatible with a control which is designed for a smaller number of banks, and a method for operating
01/12/2005CN1565034A Synchronous semiconductor storage device module and its control method, information device
01/11/2005US6842874 Method and apparatus for redundant location addressing using data compression
01/11/2005US6842840 Controller which determines presence of memory in a node of a data network
01/11/2005US6842399 Delay lock loop circuit useful in a synchronous system and associated methods
01/11/2005US6842397 Clock-synchronous semiconductor memory device
01/11/2005US6842394 Semiconductor device using SCL circuit
01/11/2005US6842393 Method for selecting one or a bank of memory devices
01/11/2005US6842392 Activation of word lines in semiconductor memory device
01/11/2005US6842384 Nonvolatile semiconductor memory with power-up read mode
01/11/2005US6842383 Method and circuit for operating a memory cell using a single charge pump
01/11/2005US6842381 Method of marginal erasure for the testing of flash memories
01/11/2005US6842376 Non-volatile semiconductor memory device for selectively re-checking word lines
01/11/2005US6842373 Command decoder and decoding method for use in semiconductor memory device
01/11/2005US6842362 Magnetic random access memory
01/11/2005US6842033 Method for controlling delay time of signal in semiconductor device
01/06/2005WO2005001899A2 Non-volatile electromechanical field effect devices and circuits using same and methods of forming same
01/06/2005WO2005001839A2 High performance gain cell architecture
01/06/2005WO2005001694A1 Data transfer method and system
01/06/2005US20050002266 Semiconductor device and its manufacturing method
01/06/2005US20050002264 Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure
01/06/2005US20050002224 Semiconductor integrated circuit device
01/06/2005US20050002221 Test key and method for validating the position of a word line overlaying a trench capacitor in DRAMs
01/06/2005US20050002220 Apparatus for flexible deactivation of word lines of dynamic memory modules and method therefor
01/06/2005US20050002215 Multiport semiconductor memory device capable of sufficiently steadily holding data and providing a sufficient write margin
01/06/2005US20050001928 Encoding device and method, decoding device and method, and image information processing system and method
01/06/2005US20050001663 Register controlled delay locked loop with reduced delay locking time
01/06/2005CA2528804A1 Non-volatile electromechanical field effect devices and circuits using same and methods of forming same
01/04/2005US6839859 Semiconductor integrated circuit having clock synchronous type circuit and clock non-synchronous type circuit