Patents
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
05/2005
05/03/2005US6888754 Nonvolatile semiconductor memory array with byte-program, byte-erase, and byte-read capabilities
04/2005
04/28/2005WO2005038811A1 Memory arrangement comprising a plurality of ram modules
04/28/2005US20050091477 Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme
04/28/2005US20050088906 Semiconductor memory device having different synchronizing timings depending on the value of CAS latency
04/28/2005US20050088903 Semiconductor memory device of hierarchy word type and sub word driver circuit
04/27/2005EP1526548A1 Improved bit line discharge method and circuit for a semiconductor memory
04/27/2005EP1525586A2 Sublithographic nanoscale memory architecture
04/27/2005EP1525585A2 Stochastic assembly of sublithographic nanoscale interfaces
04/27/2005EP1446723A4 Method employed by a base station for transferring data
04/27/2005CN1610109A Stacked semiconductor device and semiconductor chip control method
04/27/2005CN1610006A Semiconductor storage device
04/27/2005CN1199190C Memory with word line voltage control and testing method thereof
04/27/2005CN1199187C Semiconductor memory device
04/27/2005CN1199183C Redundant form address decoder for memory system
04/26/2005US6885610 Programmable delay for self-timed-margin
04/26/2005US6885609 Semiconductor memory device supporting two data ports
04/26/2005US6885608 Multi-port memory circuit
04/26/2005US6885606 Synchronous semiconductor memory device with a plurality of memory banks and method of controlling the same
04/26/2005US6885595 Memory device
04/26/2005US6885594 Method and circuit for elastic storing capable of adapting to high-speed data communications
04/26/2005US6885589 Synchronous up/down address generator for burst mode read
04/26/2005US6885216 Semiconductor circuit device having active and standby states
04/26/2005US6885092 Semiconductor device and a memory system including a plurality of IC chips in a common package
04/21/2005US20050086595 Page boundary detector
04/21/2005US20050083774 Method and apparatus for reducing power consumption in a memory array with dynamic word line driver/decoders
04/21/2005US20050083769 Low voltage operation DRAM control circuits
04/21/2005US20050083765 Multi-port static random access memory
04/21/2005US20050083763 Multiple configuration multiple chip memory device and method
04/21/2005US20050083753 Memory device
04/21/2005US20050083738 Non-volatile memory technology suitable for flash and byte operation application
04/21/2005US20050083734 Magnetic random access memory
04/21/2005US20050083731 Magnetic random access memory
04/21/2005US20050083730 Magnetic random access memory
04/21/2005US20050082664 Stacked semiconductor device and semiconductor chip control method
04/21/2005DE10317364B4 Integrierter dynamischer Speicher mit Steuerungsschaltung zur Steuerung eines Refresh-Betriebs von Speicherzellen Integrated dynamic memory control circuit for controlling a refresh operation of memory cells
04/20/2005CN1607650A Strong electrolyte film and its manufacturing method, strong electrolyte capacitor, strong electrolyte memory
04/19/2005US6882592 Semiconductor memory device
04/19/2005US6882591 Synchronous controlled, self-timed local SRAM block
04/19/2005US6882590 Multiple configuration multiple chip memory device and method
04/19/2005US6882584 Method for operating a semiconductor memory, and semiconductor memory
04/19/2005US6882581 Semiconductor integrated circuit capable of selecting lines of data bus to which data is input when the number of bits of input data is different from the number of bits of the data bus
04/19/2005US6882580 Memory devices having power supply routing for delay locked loops that counteracts power noise effects
04/19/2005US6882578 PCRAM rewrite prevention
04/19/2005US6882576 Semiconductor memory device
04/19/2005US6882562 Method and apparatus for providing pseudo 2-port RAM functionality using a 1-port memory cell
04/19/2005US6882556 Semiconductor memory having a configuration of memory cells
04/19/2005US6882193 Voltage detection circuit, power-on/off reset circuit, and semiconductor device
04/14/2005WO2005034133A1 Method and apparatus for implicit dram precharge
04/14/2005WO2004055822A3 Tamper-resisting packaging
04/14/2005US20050078546 Semiconductor memory device and method of manufacturing the same
04/14/2005US20050078545 Method and circuit for controlling generation of column selection line signal
04/14/2005US20050078544 Efficient implementation of multiple clock domain accesses to diffused memories in structured ASICs
04/14/2005US20050078543 Dual-ported read sram cell with improved soft error immunity
04/14/2005US20050078542 Memory device having multiple array structure for increased bandwidth
04/14/2005US20050078528 Group erasing system for flash array with multiple sectors
04/14/2005US20050078520 Method and device for preserving word line pass bias using ROM in NAND-type flash memory
04/14/2005US20050078517 Common wordline flash array architecture
04/14/2005US20050078514 Multiple twin cell non-volatile memory array and logic block structure and method therefor
04/14/2005US20050078503 Memory circuit with non-volatile identification memory and associated method
04/14/2005US20050077975 Circuits and methods of temperature compensation for refresh oscillator
04/14/2005DE10109318B4 Halbleiterspeichervorrichtung für schnellen Zugriff A semiconductor memory device for fast access
04/13/2005CN1606092A Method for intercrossed memory space disposition
04/13/2005CN1605993A Low power consumption fast list by employing two stage content addressing register for comparison
04/13/2005CN1197087C Synchronous semi-conductor storage
04/13/2005CN1197012C Relative allocation device and method for data storage card
04/12/2005US6879531 Reduced read delay for single-ended sensing
04/12/2005US6879527 Semiconductor memory device with structure providing increased operating speed
04/12/2005US6879518 Embedded memory with security row lock protection
04/12/2005US6879505 Word line arrangement having multi-layer word line segments for three-dimensional memory array
04/12/2005US6879200 Delay circuit, semiconductor integrated circuit device containing a delay circuit and delay method
04/07/2005WO2005031747A1 Memory device having multiple array structure for increased bandwidth
04/07/2005WO2004102576A3 Semiconductor memory device and method of operating same
04/07/2005US20050074926 Method of making non-volatile field effect devices and arrays of same
04/07/2005US20050073898 Apparatus and method for disturb-free programming of passive element memory cells
04/07/2005US20050073892 Data processing apparatus
04/06/2005EP1521474A2 Data processing apparatus
04/06/2005EP0960423B1 Reprogrammable memory device with variable page size
04/06/2005CN1604636A Data processing apparatus
04/06/2005CN1604227A 存储器模块 Memory Modules
04/06/2005CN1196133C Dram incorporating self refresh control circuit and system LSI including the dram
04/05/2005US6877100 Adjustable timing circuit of an integrated circuit by selecting and moving clock edges based on a signal propagation time stored in a programmable non-volatile fuse circuit
04/05/2005US6876596 Decoder circuit with function of plural series bit line selection
04/05/2005US6876595 Decode path gated low active power SRAM
04/05/2005US6876594 Integrated circuit with programmable fuse array
04/05/2005US6876588 Semiconductor storage device formed to optimize test technique and redundancy technology
04/05/2005US6876573 Semiconductor memory device
04/05/2005US6876567 Ferroelectric memory device and method of reading a ferroelectric memory
04/05/2005US6876563 Method for configuring chip selects in memories
04/05/2005US6876353 Shift register and electronic apparatus
03/2005
03/31/2005WO2005029498A2 Nanoscale wire coding for stochastic assembly
03/31/2005US20050071541 Method and apparatus for implicit DRAM precharge
03/31/2005US20050068843 Asynchronous pseudo sram
03/31/2005US20050068842 Electronic device, nonvolatile memory and method of overwriting data in nonvolatile memory
03/31/2005US20050068840 Methods of selectively activating word line segments enabled by row addresses and semiconductor memory devices having partial activation commands of word line
03/31/2005US20050068838 Semiconductor memory device allowing accurate burn-in test
03/31/2005US20050068836 Random access memory having driver for reduced leakage current
03/31/2005US20050068835 Memory control circuit
03/31/2005US20050068832 Semiconductor storage device
03/31/2005US20050068827 Leakage tolerant register file
03/31/2005US20050068823 Nonvolatile semiconductor memory and method for controlling the same