Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 8 - Arrangements for selecting an address in a digital store
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
11/2005
11/01/2005US6961831 Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules
11/01/2005US6961805 Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous reading writing or erasure
11/01/2005US6961296 Spatially-spectrally swept optical memories and addressing methods
11/01/2005US6961282 Semiconductor memory device with driving circuits for screening defective wordlines and related methods
11/01/2005US6961281 Single rank memory module for use in a two-rank memory module system
11/01/2005US6961280 Techniques for implementing address recycling in memory circuits
11/01/2005US6961259 Apparatus and methods for optically-coupled memory systems
11/01/2005US6960951 Circuit for detecting a logic transition with improved stability of the length of a detection signal pulse
11/01/2005CA2284681C Transmission and reception of television programmes and other data
10/2005
10/27/2005WO2005101421A1 Addressing data within dynamic random access memory
10/27/2005US20050240985 Policy engine and methods and systems for protecting data
10/27/2005US20050240791 Interleaved delay line for phase locked and delay locked loops
10/27/2005US20050238128 Duty cycle correction apparatus and method for use in a semiconductor memory device
10/27/2005US20050237851 Asynchronous, high-bandwidth memory component using calibrated timing elements
10/27/2005US20050237849 Semiconductor integrated circuit device
10/27/2005US20050237845 Data storage device and method of forming the same
10/27/2005US20050237827 RAS time control circuit and method for use in DRAM using external clock
10/27/2005US20050237820 Semiconductor integrated circuit device
10/27/2005US20050237784 Nonvolatile ferroelectric memory device with split word lines
10/27/2005US20050237778 System with meshed power and signal buses on cell array
10/27/2005US20050237106 Constant-current generating circuit
10/27/2005DE102005012356A1 Wet-etch composition for manufacturing e.g. electrode of a capacitor for semiconductor device comprises peracetic acid and fluorinated acid
10/27/2005DE102004015868A1 Rekonstruktion der Signalzeitgebung in integrierten Schaltungen Reconstruction of the signal timing in integrated circuits
10/26/2005CN1689117A Memory
10/26/2005CN1689114A Semiconductor device
10/26/2005CN1689112A Semiconductor memory
10/26/2005CN1689106A Electronic device with data storage device
10/26/2005CN1225025C Semiconductor memory
10/26/2005CN1224874C Register with memory devices installed in unlimited amount and memory module
10/25/2005US6958949 Decoding structure for a memory device with a control code
10/25/2005US6958948 Semiconductor device having a data latching or storing function
10/25/2005US6958945 Device having a memory array storing each bit in multiple memory cells
10/25/2005US6958944 Enhanced refresh circuit and method for reduction of DRAM refresh cycles
10/25/2005US6958935 Nonvolatile semiconductor memory with X8/X16 operation mode using address control
10/25/2005CA2369846C Interleaved wordline architecture
10/20/2005WO2005096796A2 Method and apparatus for a dual power supply to embedded non-volatile memory
10/20/2005US20050235066 Addressing data within dynamic random access memory
10/20/2005US20050232203 Data processing apparatus, and its processing method, program product and mobile telephone apparatus
10/20/2005US20050232068 Semiconductor memory device
10/20/2005US20050232067 Semiconductor integrated circuit device and data write method thereof
10/20/2005US20050232066 Method for characterizing cells with consideration for bumped waveform and delay time calculation method for semiconductor integrated circuits using the same
10/20/2005US20050232065 Method and circuit for controlling operation mode of PSRAM
10/20/2005US20050232064 Method of accessing word line in semiconductor device
10/20/2005US20050232063 Circuit for generating data strobe signal in DDR memory device, and method therefor
10/20/2005US20050232062 Apparatus and methods for optically-coupled memory systems
10/20/2005US20050232059 Semiconductor device with non-volatile memory and random access memory
10/20/2005US20050232057 Method and apparatus for security in a wireless network
10/20/2005US20050232056 Electronic device with data storage device
10/20/2005US20050232048 Memory device for controlling programming setup time
10/20/2005US20050232036 Semiconductor memory device and method of driving the same
10/20/2005US20050232027 Data storage device, data storage control apparatus, data storage control method, and data storage control program
10/20/2005US20050232026 Ultraviolet erasable semiconductor memory device
10/20/2005US20050232023 Method and apparatus for selecting memory cells within a memory array
10/20/2005US20050232013 Nonvolatile semiconductor memory device
10/20/2005US20050231998 Nonvolatile ferroelectric memory device with split word lines
10/20/2005US20050231991 Semiconductor device having a power down mode
10/20/2005US20050231264 Block selection circuit
10/20/2005US20050231255 Duty ratio corrector, and memory device having the same
10/20/2005US20050231248 Control circuit for delay locked loop
10/20/2005US20050231247 Delay locked loop
10/19/2005CN1685607A 高频功率放大器模块 High-frequency power amplifier module
10/18/2005US6956788 Asynchronous data structure for storing data generated by a DSP system
10/18/2005US6956786 Random access memory with optional inaccessible memory cells
10/18/2005US6956785 Method and apparatus for saving current in a memory device
10/18/2005US6956775 Write pointer error recovery
10/18/2005US6956765 Magneto-resistance effect element, magnetic memory and magnetic head
10/13/2005WO2005095895A1 Sensor comprising a surface wave component
10/13/2005US20050226091 Semiconductor memory device including internal clock doubler
10/13/2005US20050226089 Memory chip architecture having non-rectangular memory banks and method for arranging memory banks
10/13/2005US20050226088 Method and apparatus for low capacitance, high output impedance driver
10/13/2005US20050226087 Protocol structure to accelerate memory transmission
10/13/2005US20050226086 Semiconductor memory device capable of carrying out stable operation
10/13/2005US20050226085 Multi-function display data processing method and associated control device
10/13/2005US20050226084 Dual port SRAM cell
10/13/2005US20050226083 Destructive-read random access memory system buffered with destructive-read memory cache
10/13/2005US20050226082 Method of accessing matrix data with address translation circuit that enables quick serial access in row or column directions
10/13/2005US20050226081 Semiconductor memory device
10/13/2005US20050226079 Methods and apparatus for dual port memory devices having hidden refresh and double bandwidth
10/13/2005US20050226078 Semiconductor integrated circuit device including OTP memory, and method of programming OTP memory
10/13/2005US20050226070 Semiconductor memory device
10/13/2005US20050226063 Method for skip over redundancy decode with very low overhead
10/13/2005US20050226058 Data input/output (I/O) apparatus for use in memory device
10/13/2005US20050226057 Memory device for multiplexing input and output operation
10/13/2005US20050226049 NOR flash memory device and method of shortening a program time
10/13/2005US20050226042 Thin film magnetic memory device for programming required information with an element similar to a memory cell information programming method
10/12/2005EP1585137A1 Synchronous global controller for enhanced pipelining
10/12/2005CN1682199A Nonvolatile RAM and memory circuit thereof
10/12/2005CN1681045A Semiconductor integrated circuit device including OPT memory, and method of programming OPT memory
10/12/2005CN1681044A Semiconductor memory device capable of carrying out stable operation
10/12/2005CN1222951C Real-time processing method for flash storage
10/12/2005CN1222857C Circuit and method for producing internal clock signal
10/11/2005US6954401 Semiconductor memory device integrating source-coupled-logic (SCL) circuit into an address buffer and a decoder
10/11/2005US6954400 Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure
10/11/2005US6954399 Column repair circuit
10/11/2005US6954398 Semiconductor memory device including subword drivers
10/11/2005US6954395 String programmable nonvolatile memory with NOR architecture
10/11/2005US6954388 Delay locked loop control circuit
10/11/2005US6954384 Semiconductor device
10/11/2005US6954378 Nonvolatile semiconductor memory device and data write method thereof
10/11/2005US6954097 Method and apparatus for generating a sequence of clock signals
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