Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 8 - Arrangements for selecting an address in a digital store
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
07/2005
07/20/2005CN1642267A Smartcard for use with a receiver of encrypted broadcast signals, and receiver
07/20/2005CN1641617A Media diary application for use with digital device
07/19/2005US6920536 Method of accessing matrix data with address translation circuit that enables quick serial access in row or column directions
07/19/2005US6920071 Semiconductor integrated circuit device
07/19/2005US6920057 Semiconductor device that enables simultaneous read and write/read operation
07/19/2005US6919745 Ring-resister controlled DLL with fine delay line and direct skew sensing detector
07/14/2005WO2005064617A1 Data write-in method for flash memory
07/14/2005US20050154842 Address control system for a memory storage device
07/14/2005US20050154819 Memory card that supports file system interoperability
07/14/2005US20050152212 Memory controller capable of estimating memory power consumption
07/14/2005US20050152211 DRAM controller and DRAM control method
07/14/2005US20050152210 Synchronous dynamic random access memory devices having dual data rate 1 (DDR1) and DDR2 modes of operation and methods of operating same
07/14/2005US20050152209 Synchronous semiconductor memory devices and data strobe input buffers with an input buffer circuit and a detection circuit for buffering data thereto
07/14/2005US20050152207 Semiconductor device using two types of power supplies supplying different potentials
07/14/2005US20050152206 Write driver with continuous impedance match and improved common mode symmetry
07/14/2005US20050152204 Multi-port memory cells for use in FIFO applications that support data transfers between cache and supplemental memory arrays
07/14/2005US20050152170 Bit cell array for preventing coupling effect in read only memory
07/14/2005DE102004059035A1 Einprägeunterdrückungs-Schaltungsschema Einprägeunterdrückungs circuit diagram
07/14/2005DE10157874B4 Vorrichtung zum Zuführen von Steuersignalen zu Speichereinheiten und dafür angepasste Speichereinheit Device for supplying control signals to memory devices, and that are adapted to memory unit
07/13/2005CN1637952A Data strobe circuit using clock signal
07/13/2005CN1637940A Semiconductor memory device for high speed data access
07/13/2005CN1637938A 半导体存储装置 The semiconductor memory device
07/13/2005CN1637937A 半导体存储装置 The semiconductor memory device
07/13/2005CN1637933A Imprint suppression circuit scheme
07/13/2005CN1637926A Addressing circuit for a cross-point memory array including cross-point resistive elements
07/13/2005CN1637731A DRAM controller and DRAM control method
07/13/2005CN1637719A Data storage apparatus, data storage control apparatus, data storage control method, and data storage control program
07/12/2005US6917560 Reduction of capacitive effects in a semiconductor memory device
07/12/2005US6917559 Constellation mapping apparatus and method
07/12/2005US6917538 Static semiconductor memory device and method of controlling the same
07/12/2005US6917536 Memory access circuit and method for reading and writing data with the same clock signal
07/12/2005CA2284038C Broadcast and reception system, and receiver/decoder and remote controller therefor
07/07/2005US20050146976 Semiconductor memory device
07/07/2005US20050146972 Low power semiconductor memory device
07/07/2005US20050146971 Semiconductor circuit device having active and standby states
07/07/2005US20050146958 Rewrite prevention in a variable resistance memory
07/07/2005US20050146950 Method and circuit for elastic storing capable of adapting to high-speed data communications
07/07/2005US20050146365 Apparatus for generating internal clock signal
07/07/2005DE10356851A1 Shift register for configuring bits used to program logic circuits, includes master- and slave latches with analysis logic to output configuration bits
07/07/2005DE102004058603A1 Electrically erasable and programmable read only memory cell, has common source region with lightly doped drain structure whose impurity region has higher dopant concentration than region of double diffused drain structure
07/06/2005EP1412947B1 Random access decoder
07/06/2005CN1635580A 闪存介质数据写入方法 Flash media data writing method
07/05/2005US6914851 Circuit element with timing control
07/05/2005US6914850 Address buffer having (N/2) stages
07/05/2005US6914849 Method and apparatus for reducing power consumption in a memory array with dynamic word line driver/decoders
07/05/2005US6914848 Word line transistor stacking for leakage control
07/05/2005US6914847 Semiconductor memory device
07/05/2005US6914846 Flash EEprom system
07/05/2005US6914843 Memory device tester and method for testing reduced power states
07/05/2005US6914832 Semiconductor memory device with memory cell array divided into blocks
07/05/2005US6914806 Magnetic memory device
06/2005
06/30/2005US20050144419 Semiconductor memory device having advanced tag block
06/30/2005US20050141334 Circuit and method for controlling inversion of delay locked loop and delay locked loop and synchronous semiconductor memory device using the same
06/30/2005US20050141333 Latch circuit and synchronous memory including the same
06/30/2005US20050141332 Semiconductor device including a register to store a value that is representative of device type information
06/30/2005US20050141331 Write circuit of double data rate synchronous DRAM
06/30/2005US20050141330 Semiconductor memory device capable of calibrating data setup time and method for driving the same
06/30/2005US20050141329 Decoder circuit
06/30/2005US20050141328 Semiconductor memory device and method of reading data from semiconductor memory device
06/30/2005US20050141327 Decoding circuit for on die termination in semiconductor memory device and its method
06/30/2005US20050141326 Main row decoder in a semiconductor memory device
06/30/2005US20050141324 Semiconductor memory device for high speed data access
06/30/2005US20050141323 Semiconductor memory device for reducing lay-out area
06/30/2005US20050141322 Semiconductor memory device
06/30/2005US20050141318 Dual chip package
06/30/2005US20050141315 System and method for adjusting noise
06/30/2005US20050141299 Semiconductor memory device for controlling cell block with state machine
06/30/2005US20050141279 Data access circuit of semiconductor memory device
06/30/2005US20050141270 Nonvolatile memory device having circuit for stably supplying desired current during data writing
06/30/2005US20050141255 Semiconductor memory device with uniform data access time
06/30/2005US20050140969 Semiconductor memory device for reducing current consumption in operation
06/30/2005DE102004049868A1 Halbleitervorrichtung in Stapelanordnung und Steuerverfahren für Halbleiterchips Semiconductor device stack assembly and control method for semiconductor chips
06/29/2005EP1548745A1 Fast reading, low power consumption memory device and reading method thereof
06/29/2005EP1548744A1 Fast reading, low power consumption memory device and reading method thereof
06/29/2005EP1548599A2 Faster write operations to nonvolatile memory by manipulation of frequently accessed sectors
06/29/2005EP1547089A2 Reconfigurable electronic device having interconnected data storage devices
06/28/2005US6912697 Semiconductor integrated circuit device
06/28/2005US6912666 Interleaved delay line for phase locked and delay locked loops
06/28/2005US6912169 Synchronous semiconductor memory device
06/28/2005US6911846 Method and apparatus for a 1 of N signal
06/28/2005CA2403859C Multidimensional addressing architecture for electronic devices
06/23/2005WO2005057586A2 Nand memory array incorporating multiple series selection devices and method for operation of same
06/23/2005WO2005026957A3 Defect-tolerant and fault-tolerant circuit interconnections
06/23/2005US20050138273 Nonvolatile memory device capable of simultaneous erase and program of different blocks
06/23/2005US20050135183 Non-volatile semiconductor memory device and electric device with the same
06/23/2005US20050135182 Chip-to-chip communication system using an ac-coupled bus and devices employed in same
06/23/2005US20050135180 Interface command architecture for synchronous flash memory
06/23/2005US20050135179 Memory array with multiple read ports
06/23/2005US20050135178 Memory array with staged output
06/23/2005US20050135177 Memory control device and memory control method
06/23/2005US20050135176 Synchronizing memory copy operations with memory accesses
06/23/2005US20050135158 Semiconductor memory device
06/23/2005US20050135147 Conductive memory array having page mode and burst mode write capability
06/23/2005US20050135146 Addressing circuit for a cross-point memory array including cross-point resistive elements
06/23/2005US20050135145 Synchronous flash memory device and method of operating the same
06/23/2005US20050135141 FeRAM having sensing voltage control function
06/23/2005US20050134340 Data strobe circuit using clock signal
06/23/2005DE19920992B4 Verfahren für einen Zugriff auf eine Speichereinrichtung A method for accessing a memory device
06/22/2005EP1543525A2 Multi-port memory cells
06/22/2005EP1543524A2 Refresh control circuit for ics with a memory array
1 ... 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 ... 194