Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 8 - Arrangements for selecting an address in a digital store
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
10/2005
10/11/2005US6954095 Apparatus and method for generating clock signals
10/11/2005US6954094 Semiconductor memory device having partially controlled delay locked loop
10/11/2005US6953960 Semiconductor memory device
10/06/2005WO2005093758A1 Collision detection in a multi-port memory system
10/06/2005WO2005091890A2 Method and apparatus for security in a wireless network
10/06/2005US20050223303 Memory channel self test
10/06/2005US20050220205 Constellation mapping apparatus and method
10/06/2005US20050219937 Multi-strobe apparatus, testing apparatus, and adjusting method
10/06/2005US20050219935 Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions
10/06/2005US20050219934 Semiconductor device
10/06/2005US20050219933 Nonaligned access to random access memory
10/06/2005US20050219922 Semiconductor device having redundancy circuit
10/06/2005US20050219921 Semiconductor system
10/06/2005US20050219919 Reconstruction of signal timing in integrated circuits
10/06/2005US20050219903 Method and apparatus for a dual power supply to embedded non-volatile memory
10/06/2005US20050218962 Voltage switching circuit
10/06/2005DE102004011672A1 Vorrichtung zur Datensynchronisation Apparatus for data synchronization
10/05/2005EP1583273A2 Data processing apparatus, and its processing method, program product and mobile telephone apparatus
10/05/2005CN1679116A PCRAM rewrite prevention
10/05/2005CN1679111A Device writing to a plurality of rows in a memory matrix simultaneously
10/05/2005CN1679011A Method and apparatus for optimizing timing for a multi-drop bus
10/05/2005CN1677863A Digital DLL device, digital DLL control method, and digital DLL control program
10/05/2005CN1677572A Nonvolatile semiconductor memory device
10/05/2005CN1677566A Dual port sram cell
10/05/2005CN1677557A Flexible multi-area memory and electronic device using the same
10/05/2005CN1677556A Partial dual-port memory and electronic device using the same
10/05/2005CN1677555A Data storage unit, data storage controlling apparatus and method, and data storage controlling program
10/05/2005CN1677480A Multi-function display data processing method and associated control device
10/05/2005CN1677368A Data processing apparatus, and its processing method, program product and mobile telephone apparatus
10/04/2005US6952368 Semiconductor device with non-volatile memory and random access memory
10/04/2005US6952363 Semiconductor memory device with selectively connectable segmented bit line member and method of driving the same
10/04/2005US6952361 Volumetric data storage apparatus
09/2005
09/29/2005WO2003098634A3 Magnetoresistive memory cell array and mram memory comprising such array
09/29/2005US20050213421 Non-volatile memory device architecture, for instance a flash kind, having a serial communication interface
09/29/2005US20050213418 Non-volatile memory device and inspection method for non-volatile memory device
09/29/2005US20050213417 Circuit arrangement for latency regulation
09/29/2005US20050213415 Static memory cell and SRAM device
09/29/2005US20050213383 Nonvolatile semiconductor memory
09/29/2005US20050213378 Method of reading multi-level nand flash memory cell and circuit for the same
09/29/2005US20050212574 Digital DLL device, digital DLL control method, and digital DLL control program
09/29/2005DE102004009692A1 Halbleiterspeichervorrichtung A semiconductor memory device
09/28/2005EP1579483A2 System and method for expanding a pulse width
09/28/2005CN1675718A Row decoder circuit for use in programming a memory device
09/28/2005CN1675717A Multi-port memory cells
09/28/2005CN1675708A Disc with temporary disc definition structure (TDDS) and temporary defect list (TDFL), and method of and apparatus for managing defect in the same
09/28/2005CN1674157A Non-volatile semiconductor memory device and writing method therefor
09/28/2005CN1674153A Methods and circuits for latency control in accessing memory devices
09/27/2005US6950370 Synchronous memory device for preventing erroneous operation due to DQS ripple
09/27/2005US6950363 Semiconductor memory device
09/27/2005US6950340 Asymmetric band-gap engineered nonvolatile memory device
09/27/2005US6950330 Addressing of memory matrix
09/27/2005US6950328 Imprint suppression circuit scheme
09/27/2005US6950325 Cascade-connected ROM
09/27/2005US6950324 Memory device composed of a plurality of memory chips in a single package
09/22/2005WO2005088642A1 Semiconductor memory
09/22/2005US20050210175 Memory module capable of improving the integrity of signals transmitted through a data bus and a command/address bus, and a memory system including the same
09/22/2005US20050207266 Semiconductor integrated circuit device
09/22/2005US20050207263 Magnetic non-volatile memory element
09/22/2005US20050207261 Common-mode current feedback amplifiers
09/22/2005US20050207260 Current feedback amplifiers with separate common-mode and differential-mode inputs
09/22/2005US20050207259 Non-volatile semiconductor memory device and writing method therefor
09/22/2005US20050207252 Semiconductor storage device, test method therefor, and test circuit therefor
09/22/2005US20050207247 Semiconductor device that enables simultaneous read and write/read operation
09/22/2005US20050207245 Bank selectable parallel test circuit and parallel test method thereof
09/22/2005US20050207230 Method for erasing/programming a non-volatile electrically erasable memory
09/22/2005US20050207229 Nonvolatile semiconductor memory
09/22/2005US20050206955 Image memory architecture for achieving high speed access
09/22/2005US20050206430 Skew detection device
09/22/2005DE10323863B4 Integrierte Schaltung und Verfahren zum Betreiben einer integrierten Schaltung Integrated circuit and method for operating an integrated circuit
09/22/2005DE102004032478A1 Verzögerungsregelkreis in Halbleiterspeichervorrichtung und sein Taktsynchronisierverfahren Delay control circuit in semiconductor memory device and its Taktsynchronisierverfahren
09/22/2005DE102004009958B3 Schaltungsanordnung zur Latenzregelung Circuit arrangement for latency control
09/21/2005EP1576611A2 Tamper-resistant packaging and approach
09/21/2005EP1576609A2 Method of address individual memory devices on a memory module
09/21/2005EP0808512B1 Method of driving a field effect transistor
09/20/2005US6948028 Destructive-read random access memory system buffered with destructive-read memory cache
09/20/2005US6947350 Synchronous controlled, self-timed local SRAM block
09/20/2005US6947349 Apparatus and method for producing an output clock pulse and output clock generator using same
09/20/2005US6947348 Gain cell memory having read cycle interlock
09/20/2005US6947340 Memory device for reducing skew of data and address
09/20/2005US6947337 Random-access memory devices comprising a dioded buffer
09/20/2005US6947334 Semiconductor memory device capable of calibrating data setup time and method for driving the same
09/20/2005US6947329 Method for detecting a resistive path or a predetermined potential in non-volatile memory electronic devices
09/20/2005US6947327 Nonvolatile memory and method of driving the same
09/20/2005US6947321 Organic thin-film switching memory device and memory device
09/20/2005US6947308 Embedded semiconductor memory with crossbar wirings and switches for high bandwidth
09/20/2005US6947100 High speed video frame buffer
09/20/2005US6946888 Percent-of-clock delay circuits with enhanced phase jitter immunity
09/20/2005US6946678 Test key for validating the position of a word line overlaying a trench capacitor in DRAMs
09/15/2005US20050204101 Partial dual-port memory and electronic device using the same
09/15/2005US20050204100 Flexible multi-area memory and electronic device using the same
09/15/2005US20050201195 Processor for processing a program
09/15/2005US20050201194 Data processing system, data processing method, and data processing program
09/15/2005US20050201193 Semiconductor integrated circuit device
09/15/2005US20050201192 Memory control apparatus for synchronous memory unit with switched on/off clock signal
09/15/2005US20050201191 Data synchronization arrangement
09/15/2005US20050201187 Integrated read-only memory, method for operating said read-only memory and corresponding production method
09/15/2005US20050201186 Semiconductor integrated circuit device
09/15/2005US20050201185 Semiconductor memory device
09/15/2005US20050201183 Column address path circuit and method for memory devices having a burst access mode
09/15/2005US20050201164 Memory device having asynchronous/synchronous operating modes
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