Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 8 - Arrangements for selecting an address in a digital store
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
12/2005
12/22/2005US20050281121 Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure
12/22/2005US20050281120 Memory system, method and predeconding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure
12/22/2005US20050281119 Method of designing semiconductor integrated circuit device and semiconductor integrated circuit device
12/22/2005US20050281118 Integrated semiconductor memory comprising at least one word line and comprising a multiplicity of memory cells
12/22/2005US20050281117 Nonvolatile semiconductor memory device
12/22/2005US20050281116 Digital memory
12/22/2005US20050281091 Fast memory
12/22/2005US20050281090 Memory architecture with segmented writing lines
12/22/2005US20050281080 Magnetic random access memory array having bit/word lines for shared write select and read operations
12/22/2005US20050281077 Semiconductor memory device
12/22/2005US20050281071 Word line driver circuits for use in semiconductor memory and driving method thereof
12/22/2005US20050280479 Circuits and methods of temperature compensation for refresh oscillator
12/22/2005US20050280461 Level shifter circuit with stress test function
12/22/2005DE102004025899A1 Electronic control arrangement, has control module with control units e.g. dynamic random access memories, having decoder units to decode bit string of signal, and connecting wire to connect each control unit with signal producing unit
12/21/2005EP1607979A2 Memory architecture with segmented write lines
12/21/2005CN1232986C Internal voltage level control circuit and semiconductor memory device and their control method
12/20/2005US6978342 Moving sectors within a block of information in a flash memory mass storage architecture
12/20/2005US6977865 Method and circuit for controlling operation mode of PSRAM
12/20/2005US6977863 Device and method for decoding an address word into word-line signals
12/20/2005US6977862 Address decoding circuit and method for addressing a regular memory area and a redundant memory area in a memory circuit
12/20/2005US6977861 Nonvolatile semiconductor memory device
12/20/2005US6977860 SRAM power reduction
12/20/2005US6977848 Data output control circuit
12/20/2005US6977840 Storage element with a defined number of write cycles
12/20/2005US6977836 Memory device that can be irreversibly programmed electrically
12/15/2005WO2005071529A3 Memory card that supports file system interoperability
12/15/2005WO2005024834A3 Low voltage operation dram control circuits
12/15/2005US20050276151 Integrated memory controller
12/15/2005US20050276150 Memory agent core clock aligned to lane
12/15/2005US20050276148 Semiconductor storage device interrupt control circuit
12/15/2005US20050276147 Semiconductor storage device and method of selecting bit line of the semiconductor storage device
12/15/2005US20050276146 Semiconductor memory device
12/15/2005US20050276138 Semiconductor memory device
12/15/2005US20050276128 Redundancy circuits and memory devices having a twist bitline scheme and methods of repairing defective cells in the same
12/15/2005US20050276100 Method and system for optimizing the number of word line segments in a segmented MRAM array
12/15/2005DE19600049B4 Selbstbootstrapvorrichtung Selbstbootstrapvorrichtung
12/14/2005EP1604370A1 Method and apparatus for establishing and maintaining desired read latency in high-speed dram
12/14/2005CN1708809A Reconfigurable electronic device having interconnected data storage devices
12/14/2005CN1707697A Method for programming a memory arrangement and programmed memory arrangement
12/14/2005CN1707690A Semiconductor memory device having a global data bus
12/14/2005CN1231722C Function switching method, function switching apparatus, data storage method, data storage apparatus, device, and air conditioner
12/13/2005US6976201 Method and system for host handling of communications errors
12/13/2005US6975558 Integrated circuit device
12/13/2005US6975554 Method and system for providing a shared write driver
12/13/2005US6975553 Nonaligned access to random access memory
12/13/2005US6975527 Memory device layout
12/08/2005US20050273552 Method and apparatus for reading and writing to solid-state memory
12/08/2005US20050270893 Phase detector for all-digital phase locked and delay locked loops
12/08/2005US20050270892 Synchronous memory device with reduced power consumption
12/08/2005US20050270891 Backwards-compatible memory module
12/08/2005US20050270889 Dynamic random access memory (DRAM) capable of canceling out complimentary noise development in plate electrodes of memory cell capacitors
12/08/2005US20050270887 Magnetic random access memory
12/08/2005US20050270886 Ferroelectric memory device and read control method thereof
12/08/2005US20050270885 Semiconductor memory device
12/08/2005US20050270884 Memory circuit, and method for reading out data contained in the memory circuit using shared command signals
12/08/2005US20050270883 Memory device with reduced word line resistance
12/08/2005US20050270817 Semiconductor memory device having first and second memory cell arrays and a program method thereof
12/08/2005US20050270074 Power-gating system and method for integrated circuit devices
12/08/2005DE10335618B4 Halbleiterspeicher und Verfahren zum Betreiben eines Halbleiterspeichers A semiconductor memory and method of operating a semiconductor memory
12/08/2005DE102004023985A1 Electronic storage component, formed by producing a crystalline silicon wall and a polysilicon wall on a substrate, covering the walls, forming troughs, and applying an insulating layer
12/07/2005EP1603136A2 Semiconductor memory device
12/07/2005CN1231061C Broadcast and reception system, and conditional access system therefor
12/07/2005CN1230828C One-shot signal generating circuit
12/07/2005CN1230827C Method for regulating threshold value of FIFO buffer
12/06/2005US6973603 Method and apparatus for optimizing timing for a multi-drop bus
12/06/2005US6973009 Semiconductor memory device capable of switching between an asynchronous normal mode and a synchronous mode and method thereof
12/06/2005US6973008 Apparatus for flexible deactivation of word lines of dynamic memory modules and method therefor
12/06/2005US6973007 Main row decoder in a semiconductor memory device
12/06/2005US6973006 Predecode column architecture and method
12/06/2005US6972996 Pattern layout of transfer transistors employed in row decoder
12/06/2005US6972609 Semiconductor integrated circuit device with a plurality of internal circuits operable in synchronism with internal clock
12/06/2005US6972450 SRAM cell design for soft error rate immunity
12/01/2005US20050268023 Multi-port random access memory
12/01/2005US20050265118 Method for controlling time point for data output in synchronous memory device
12/01/2005US20050265117 Apparatus and method for generating clock signals
12/01/2005US20050265115 Compact decode and multiplexing circuitry for a multi-port memory having a common memory interface
12/01/2005US20050265114 Nonvolatile memory, semiconductor device, and method of programming to nonvolatile memory
12/01/2005US20050265111 High voltage generation and regulation circuit in a memory device
12/01/2005US20050265110 Circuit and method for generating word line control signals and semiconductor memory device having the same
12/01/2005US20050265109 Nonvolatile semiconductor memory
12/01/2005US20050265108 Memory controller which increases bus bandwidth, data transmission method using the same, and computer system having the same
12/01/2005US20050265107 Semiconductor memory device
12/01/2005US20050265106 Compact decode and multiplexing circuitry for a multi-port memory having a common memory interface
12/01/2005US20050265060 Adjustable timing circuit of an integrated circuit
12/01/2005DE102004031450A1 Verzögerungsregelkreis-Vorrichtung Delay locked loop device
12/01/2005DE102004022326A1 Verfahren zum Testen eines integrierten Halbleiterspeichers A method for testing an integrated semiconductor memory,
11/2005
11/30/2005EP1600978A1 Semiconductor memory device and signal processing system
11/30/2005CN1703759A Semiconductor storage device, test method therefor, and test circuit therefor
11/30/2005CN1702767A Enhanced refresh circuit and method for reduction of dram refresh cycles
11/30/2005CN1229880C Magnetic resistance element
11/30/2005CN1229813C Shift register and electronic device
11/30/2005CN1229812C Shift register with selective multiple shifts
11/30/2005CN1229809C Flash memory equipment for word line driver having reading mode and operation method thereof
11/29/2005US6970391 Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions
11/29/2005US6969633 Lower electrode isolation in a double-wide trench and method of making same
11/24/2005WO2005112333A1 Policy engine and methods and systems for protecting data
11/24/2005WO2005112039A1 Latched programming of memory and method
11/24/2005WO2005111822A2 Method and device for managing a bus
11/24/2005WO2005093758A8 Collision detection in a multi-port memory system
11/24/2005US20050262295 Content addressable memory with programmable word width and programmable priority
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